KMAC/MASKED Simulation Results

Tuesday March 12 2024 19:02:37 UTC

GitHub Revision: `bc285b7382`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 8078106501385188224785993882809517173695187907049792415947230968390919037084

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.796m	19.289ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.170s	222.217us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.290s	378.627us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	20.960s	2.933ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.640s	594.760us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.740s	189.382us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.290s	378.627us	20	20	100.00
		kmac_csr_aliasing	7.640s	594.760us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.750s	27.350us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.540s	82.787us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	57.272m	122.368ms	50	50	100.00
V2	burst_write	kmac_burst_write	27.713m	15.646ms	47	50	94.00
V2	test_vectors	kmac_test_vectors_sha3_224	43.137m	119.270ms	50	50	100.00
		kmac_test_vectors_sha3_256	45.857m	1.048s	50	50	100.00
		kmac_test_vectors_sha3_384	33.992m	302.616ms	50	50	100.00
		kmac_test_vectors_sha3_512	25.195m	208.530ms	48	50	96.00
		kmac_test_vectors_shake_128	1.817h	2.497s	49	50	98.00
		kmac_test_vectors_shake_256	1.641h	886.839ms	50	50	100.00
		kmac_test_vectors_kmac	7.490s	4.480ms	48	50	96.00
		kmac_test_vectors_kmac_xof	8.340s	525.883us	50	50	100.00
V2	sideload	kmac_sideload	10.477m	89.516ms	50	50	100.00
V2	app	kmac_app	7.452m	200.000ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.382m	98.759ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	8.092m	69.734ms	50	50	100.00
V2	error	kmac_error	8.658m	14.363ms	49	50	98.00
V2	key_error	kmac_key_error	7.060s	1.988ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	46.980s	2.410ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	31.140s	445.553us	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.410m	20.618ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	45.750s	2.623ms	50	50	100.00
V2	stress_all	kmac_stress_all	44.987m	414.351ms	45	50	90.00
V2	intr_test	kmac_intr_test	0.880s	14.466us	50	50	100.00
V2	alert_test	kmac_alert_test	0.920s	63.225us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.400s	119.729us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.400s	119.729us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.170s	222.217us	5	5	100.00
		kmac_csr_rw	1.290s	378.627us	20	20	100.00
		kmac_csr_aliasing	7.640s	594.760us	5	5	100.00
		kmac_same_csr_outstanding	2.800s	123.079us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.170s	222.217us	5	5	100.00
		kmac_csr_rw	1.290s	378.627us	20	20	100.00
		kmac_csr_aliasing	7.640s	594.760us	5	5	100.00
		kmac_same_csr_outstanding	2.800s	123.079us	20	20	100.00
V2		TOTAL			1035	1050	98.57
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.470s	300.158us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.470s	300.158us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.470s	300.158us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.470s	300.158us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.110s	1.667ms	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.780m	27.684ms	5	5	100.00
		kmac_tl_intg_err	6.080s	3.816ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	6.080s	3.816ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	45.750s	2.623ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.796m	19.289ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	10.477m	89.516ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.470s	300.158us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.780m	27.684ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.780m	27.684ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.780m	27.684ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.796m	19.289ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	45.750s	2.623ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.780m	27.684ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.963m	5.558ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.796m	19.289ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	52.418m	82.841ms	18	50	36.00
V3		TOTAL			18	50	36.00
		TOTAL			1243	1290	96.36

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	18	72.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.10	98.10	92.66	99.89	96.36	95.91	98.89	97.89

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:827) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 25 failures:
- Test kmac_stress_all_with_rand_reset has 25 failures.
  - 3.kmac_stress_all_with_rand_reset.48709485708608477551609429640523032230262469743085207045873968601897216745427
    Line 612, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 50986904725 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 50986904725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.kmac_stress_all_with_rand_reset.35301076670860298832018075788907529475555799963960418704377253224997377126585
    Line 274, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2446491640 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2446491640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 23 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 6 failures:

Test kmac_test_vectors_kmac has 2 failures.

2.kmac_test_vectors_kmac.85693993345298670289768606742887450237123475113937453587556175031752997076627
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_test_vectors_kmac/latest/run.log

  UVM_ERROR @  35944173 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  35944173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

20.kmac_test_vectors_kmac.49156796217302644834419679473420495922757833515582542886627422286277312357896
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/20.kmac_test_vectors_kmac/latest/run.log

  UVM_ERROR @ 112852490 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 112852490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 1 failures.

4.kmac_stress_all.48947196610393973224697923808156788613822913996223981561657973016952087678606
Line 1002, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_stress_all/latest/run.log

  UVM_ERROR @ 23754238387 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 23754238387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_test_vectors_shake_128 has 1 failures.

8.kmac_test_vectors_shake_128.66654231290001896617870209225628009295552044414626829709821392132368126811733
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_test_vectors_shake_128/latest/run.log

  UVM_ERROR @ 109184671 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 109184671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_test_vectors_sha3_512 has 2 failures.

35.kmac_test_vectors_sha3_512.49632673518495375541199835178593880581331415395173602272354245896513990353662
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/35.kmac_test_vectors_sha3_512/latest/run.log

  UVM_ERROR @  33115554 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  33115554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

49.kmac_test_vectors_sha3_512.39468835616270450320589185814746423359058495335530607205336074951085192377967
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/49.kmac_test_vectors_sha3_512/latest/run.log

  UVM_ERROR @  55595368 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  55595368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 6 failures:
- Test kmac_stress_all_with_rand_reset has 6 failures.
  - 7.kmac_stress_all_with_rand_reset.82098566608804556237026196491521529995980848997987055555843188856877855004404
    Line 262, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  83919581 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483760 [0x80000070]) reg name: kmac_reg_block.err_code
  UVM_INFO @  83919581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 12.kmac_stress_all_with_rand_reset.41740037454170500032561615516542164018441125289701652224740373790299308175210
    Line 1263, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 41888865023 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483736 [0x80000058]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 41888865023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 5 failures:
- Test kmac_stress_all has 3 failures.
  - 11.kmac_stress_all.20409875620559514068648074178225980791735236985622303567232325305912329389067
    Line 731, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 37930629899 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 37930629899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 44.kmac_stress_all.80269810245608319910382173849260013885702785551583311775976973240472605208134
    Line 1553, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/44.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 41341673493 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 41341673493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test kmac_error has 1 failures.
  - 20.kmac_error.3555946957389991370887528435664314674464103556869492628125801829384718439359
    Line 689, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/20.kmac_error/latest/run.log
```
  UVM_FATAL @ 10052122067 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 10052122067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 44.kmac_stress_all_with_rand_reset.55206454450948755241154941989978329651692130738481318574549282252385872587058
    Line 3264, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/44.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 284956725454 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 284956725454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
- Test kmac_app has 1 failures.
  - 8.kmac_app.16572039714954063552230183702904290500411345003511507352247691583400472854509
    Line 1158, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_app/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_burst_write has 3 failures.
  - 12.kmac_burst_write.73304567632017191324767676020487566564258721852859262674317970011096760460042
    Line 885, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 23.kmac_burst_write.15024117187178968224918762212168485381818719459383672831822843770050067109397
    Line 584, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 1 failures:
- Test kmac_stress_all has 1 failures.
  - 45.kmac_stress_all.110604694625353892532681700664509257068940038408781392600585912215778420668860
    Line 797, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/45.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 41719268483 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (90 [0x5a] vs 4 [0x4]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 41719268483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```