e844018f2c| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | kmac_smoke | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | kmac_csr_hw_reset | 1.120s | 18.384us | 5 | 5 | 100.00 |
| V1 | csr_rw | kmac_csr_rw | 1.250s | 177.132us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | kmac_csr_bit_bash | 23.470s | 5.765ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | kmac_csr_aliasing | 9.230s | 1.810ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | kmac_csr_mem_rw_with_rand_reset | 2.870s | 388.860us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | kmac_csr_rw | 1.250s | 177.132us | 20 | 20 | 100.00 |
| kmac_csr_aliasing | 9.230s | 1.810ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | kmac_mem_walk | 0.760s | 17.831us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | kmac_mem_partial_access | 1.520s | 128.950us | 5 | 5 | 100.00 |
| V1 | TOTAL | 65 | 115 | 56.52 | |||
| V2 | long_msg_and_output | kmac_long_msg_and_output | 0 | 50 | 0.00 | ||
| V2 | burst_write | kmac_burst_write | 0 | 50 | 0.00 | ||
| V2 | test_vectors | kmac_test_vectors_sha3_224 | 0 | 50 | 0.00 | ||
| kmac_test_vectors_sha3_256 | 0 | 50 | 0.00 | ||||
| kmac_test_vectors_sha3_384 | 0 | 50 | 0.00 | ||||
| kmac_test_vectors_sha3_512 | 0 | 50 | 0.00 | ||||
| kmac_test_vectors_shake_128 | 0 | 50 | 0.00 | ||||
| kmac_test_vectors_shake_256 | 0 | 50 | 0.00 | ||||
| kmac_test_vectors_kmac | 0 | 50 | 0.00 | ||||
| kmac_test_vectors_kmac_xof | 0 | 50 | 0.00 | ||||
| V2 | sideload | kmac_sideload | 0 | 50 | 0.00 | ||
| V2 | app | kmac_app | 0 | 50 | 0.00 | ||
| V2 | app_with_partial_data | kmac_app_with_partial_data | 0 | 10 | 0.00 | ||
| V2 | entropy_refresh | kmac_entropy_refresh | 0 | 50 | 0.00 | ||
| V2 | error | kmac_error | 0 | 50 | 0.00 | ||
| V2 | key_error | kmac_key_error | 0 | 50 | 0.00 | ||
| V2 | edn_timeout_error | kmac_edn_timeout_error | 0 | 20 | 0.00 | ||
| V2 | entropy_mode_error | kmac_entropy_mode_error | 0 | 20 | 0.00 | ||
| V2 | entropy_ready_error | kmac_entropy_ready_error | 0 | 10 | 0.00 | ||
| V2 | lc_escalation | kmac_lc_escalation | 0 | 50 | 0.00 | ||
| V2 | stress_all | kmac_stress_all | 0 | 50 | 0.00 | ||
| V2 | intr_test | kmac_intr_test | 0.880s | 18.492us | 50 | 50 | 100.00 |
| V2 | alert_test | kmac_alert_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | kmac_tl_errors | 4.150s | 968.916us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | kmac_tl_errors | 4.150s | 968.916us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | kmac_csr_hw_reset | 1.120s | 18.384us | 5 | 5 | 100.00 |
| kmac_csr_rw | 1.250s | 177.132us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 9.230s | 1.810ms | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 2.830s | 429.406us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | kmac_csr_hw_reset | 1.120s | 18.384us | 5 | 5 | 100.00 |
| kmac_csr_rw | 1.250s | 177.132us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 9.230s | 1.810ms | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 2.830s | 429.406us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 90 | 1050 | 8.57 | |||
| V2S | shadow_reg_update_error | kmac_shadow_reg_errors | 1.430s | 103.723us | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | kmac_shadow_reg_errors | 1.430s | 103.723us | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | kmac_shadow_reg_errors | 1.430s | 103.723us | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | kmac_shadow_reg_errors | 1.430s | 103.723us | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | kmac_shadow_reg_errors_with_csr_rw | 3.070s | 1.119ms | 19 | 20 | 95.00 |
| V2S | tl_intg_err | kmac_sec_cm | 0 | 5 | 0.00 | ||
| kmac_tl_intg_err | 5.530s | 1.669ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | kmac_tl_intg_err | 5.530s | 1.669ms | 20 | 20 | 100.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | kmac_lc_escalation | 0 | 50 | 0.00 | ||
| V2S | sec_cm_sw_key_key_masking | kmac_smoke | 0 | 50 | 0.00 | ||
| V2S | sec_cm_key_sideload | kmac_sideload | 0 | 50 | 0.00 | ||
| V2S | sec_cm_cfg_shadowed_config_shadow | kmac_shadow_reg_errors | 1.430s | 103.723us | 20 | 20 | 100.00 |
| V2S | sec_cm_fsm_sparse | kmac_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_ctr_redun | kmac_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_packer_ctr_redun | kmac_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_cfg_shadowed_config_regwen | kmac_smoke | 0 | 50 | 0.00 | ||
| V2S | sec_cm_fsm_global_esc | kmac_lc_escalation | 0 | 50 | 0.00 | ||
| V2S | sec_cm_fsm_local_esc | kmac_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_absorbed_ctrl_mubi | kmac_mubi | 0 | 10 | 0.00 | ||
| V2S | sec_cm_sw_cmd_ctrl_sparse | kmac_smoke | 0 | 50 | 0.00 | ||
| V2S | TOTAL | 59 | 75 | 78.67 | |||
| V3 | throughput | kmac_throughput | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | kmac_stress_all_with_rand_reset | 0 | 50 | 0.00 | ||
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| TOTAL | 214 | 1290 | 16.59 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 25 | 25 | 3 | 12.00 |
| V2S | 5 | 5 | 2 | 40.00 |
| V3 | 2 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 43.42 | 34.14 | 57.11 | 11.73 | 0.00 | 38.97 | 100.00 | 61.97 |
launch_task.returncode != *, err: * *:*:* * lswatcher.go:*] Failed to connect to Watcher service in the Envelope (you probably need to import _ "google3/tech/env/go/envelope"): generic::unimplemented: envrpc: no envelope available for service "chubby.googleapis.com" Failure to submit jobs: rpc error: code = Unavailable desc = The service is currently unavailable. has 538 failures:
0.kmac_smoke.112346335483714898005491357709228427849681808973818271274054939272934057322539
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_smoke/latest/run.log
1.kmac_smoke.43411779201771136301188835173580714144078431677121265943577769098469136411371
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_smoke/latest/run.log
... and 6 more failures.
0.kmac_sideload.91839730525792281590092840480511022261276662655089379074803336899562597206292
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_sideload/latest/run.log
1.kmac_sideload.85709443098493656063796493692773846708329150249699908221879861195479330121108
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_sideload/latest/run.log
... and 6 more failures.
0.kmac_test_vectors_sha3_224.108737534820057781691955254915073065072799551152051199495901592877066596185660
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_224/latest/run.log
1.kmac_test_vectors_sha3_224.109725049430217102999172348107020314485408286462517236203497772496819471897599
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_224/latest/run.log
... and 6 more failures.
0.kmac_test_vectors_sha3_384.16590828839367427413296095565500727012786664950885382598203214403535724346178
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_384/latest/run.log
1.kmac_test_vectors_sha3_384.57845034241355854951752800657636393665018453097792131279665335894865018957651
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_384/latest/run.log
... and 6 more failures.
0.kmac_test_vectors_shake_128.85755718600409139609611138374063227918760648773613432262701829744598113602267
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_test_vectors_shake_128/latest/run.log
1.kmac_test_vectors_shake_128.24312919010868292117757343853246533392940097402275607319206265368333371741025
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_test_vectors_shake_128/latest/run.log
... and 6 more failures.
Job killed most likely because its dependent job failed. has 537 failures:
0.kmac_long_msg_and_output.112137121030350939045153224018692908920864059108374137298939630885690130299045
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_long_msg_and_output/latest/run.log
1.kmac_long_msg_and_output.70192161138187623735279002076395402489938762962821304285814999983745570524691
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_long_msg_and_output/latest/run.log
... and 6 more failures.
0.kmac_burst_write.12709934925848586716443850563034862003194551856529998319143718574534078901113
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_burst_write/latest/run.log
1.kmac_burst_write.11984704057982871952198229981906748128009889789583388288999825330033348986073
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_burst_write/latest/run.log
... and 6 more failures.
0.kmac_test_vectors_sha3_256.26489077423681590912944743117816515348306290289404710968985173366817630946870
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_256/latest/run.log
1.kmac_test_vectors_sha3_256.72978354269441745107134076140120509433816789234541231972341229304501662243763
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_256/latest/run.log
... and 6 more failures.
0.kmac_test_vectors_sha3_512.11153837620526348061534078706589625678900897497851348175853148012245551375953
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_512/latest/run.log
1.kmac_test_vectors_sha3_512.105405287891504593599812743568441950764583233229729550383696589391222346044464
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_512/latest/run.log
... and 6 more failures.
0.kmac_test_vectors_shake_256.29225167843980163080784759429522525710599101616412903695708073441750485639884
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_test_vectors_shake_256/latest/run.log
1.kmac_test_vectors_shake_256.34350807030382041834952627389228475548690893609076233308081121497141392299660
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_test_vectors_shake_256/latest/run.log
... and 6 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_* reset value: * has 1 failures:
16.kmac_shadow_reg_errors_with_csr_rw.55263734328290076398626602059602472311100586830504233875421488310701844405274
Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
UVM_ERROR @ 318325033 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (4215345027 [0xfb410f83] vs 1141249192 [0x440614a8]) Regname: kmac_reg_block.prefix_3 reset value: 0x0
UVM_INFO @ 318325033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---