KMAC/MASKED Simulation Results

Sunday March 17 2024 19:02:52 UTC

GitHub Revision: `c187a82ee8`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 28440605375541353837496064678278045899395893237469128852560697715229879921060

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.588m	4.942ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.210s	65.319us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.250s	112.509us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	19.810s	965.768us	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.580s	1.459ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.750s	85.984us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.250s	112.509us	20	20	100.00
		kmac_csr_aliasing	10.580s	1.459ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.780s	15.293us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.570s	112.067us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	57.531m	1.112s	50	50	100.00
V2	burst_write	kmac_burst_write	28.709m	22.951ms	48	50	96.00
V2	test_vectors	kmac_test_vectors_sha3_224	46.941m	1.190s	48	50	96.00
		kmac_test_vectors_sha3_256	42.726m	696.459ms	50	50	100.00
		kmac_test_vectors_sha3_384	32.628m	1.395s	49	50	98.00
		kmac_test_vectors_sha3_512	26.440m	670.925ms	50	50	100.00
		kmac_test_vectors_shake_128	1.875h	2.930s	50	50	100.00
		kmac_test_vectors_shake_256	1.614h	1.392s	50	50	100.00
		kmac_test_vectors_kmac	7.400s	1.029ms	50	50	100.00
		kmac_test_vectors_kmac_xof	7.020s	650.515us	50	50	100.00
V2	sideload	kmac_sideload	10.104m	75.895ms	50	50	100.00
V2	app	kmac_app	7.459m	24.228ms	47	50	94.00
V2	app_with_partial_data	kmac_app_with_partial_data	7.359m	42.577ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.846m	10.975ms	49	50	98.00
V2	error	kmac_error	7.378m	109.249ms	48	50	96.00
V2	key_error	kmac_key_error	11.130s	20.952ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	1.074m	11.055ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	53.960s	6.419ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.342m	7.648ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	1.098m	980.361us	50	50	100.00
V2	stress_all	kmac_stress_all	59.129m	37.915ms	48	50	96.00
V2	intr_test	kmac_intr_test	0.920s	20.906us	50	50	100.00
V2	alert_test	kmac_alert_test	1.000s	58.275us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.530s	111.422us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.530s	111.422us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.210s	65.319us	5	5	100.00
		kmac_csr_rw	1.250s	112.509us	20	20	100.00
		kmac_csr_aliasing	10.580s	1.459ms	5	5	100.00
		kmac_same_csr_outstanding	2.640s	223.213us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.210s	65.319us	5	5	100.00
		kmac_csr_rw	1.250s	112.509us	20	20	100.00
		kmac_csr_aliasing	10.580s	1.459ms	5	5	100.00
		kmac_same_csr_outstanding	2.640s	223.213us	20	20	100.00
V2		TOTAL			1037	1050	98.76
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.550s	67.777us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.550s	67.777us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.550s	67.777us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.550s	67.777us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.110s	132.095us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.964m	9.402ms	5	5	100.00
		kmac_tl_intg_err	5.710s	964.133us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.710s	964.133us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.098m	980.361us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.588m	4.942ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	10.104m	75.895ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.550s	67.777us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.964m	9.402ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.964m	9.402ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.964m	9.402ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.588m	4.942ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.098m	980.361us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.964m	9.402ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	7.397m	56.793ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.588m	4.942ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	55.146m	39.572ms	13	50	26.00
V3		TOTAL			13	50	26.00
		TOTAL			1240	1290	96.12

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	18	72.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.97	98.10	92.69	99.89	95.45	95.91	98.89	97.89

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:827) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 34 failures:
- Test kmac_stress_all_with_rand_reset has 34 failures.
  - 1.kmac_stress_all_with_rand_reset.60830157577610217579145186367478923547957818793435291779706348589091756046970
    Line 1394, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 87239799931 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 87239799931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.kmac_stress_all_with_rand_reset.94466550834331712975368889078174958516040332270383467553493396442361203364303
    Line 934, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 90416814113 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 90416814113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 32 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
- Test kmac_burst_write has 2 failures.
  - 9.kmac_burst_write.104194938548571005055601517689514104590437548500646254218888606940775373899523
    Line 584, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 20.kmac_burst_write.22055984115642352247000840439375297170318880782108552567509385085363892627233
    Line 752, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/20.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_error has 1 failures.
  - 39.kmac_error.34867174710700437967191010065135663904139973251097266868697460492731991416105
    Line 997, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/39.kmac_error/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_entropy_refresh has 1 failures.
  - 42.kmac_entropy_refresh.73380049133829626758283668349023574485383581814517300734963793341483161618297
    Line 1026, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/42.kmac_entropy_refresh/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 3 failures:
- Test kmac_error has 1 failures.
  - 1.kmac_error.38245238730685358647354241915706969825266193085864388678411770215128698969123
    Line 430, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_error/latest/run.log
```
  UVM_FATAL @ 10368126309 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 10368126309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_stress_all has 2 failures.
  - 32.kmac_stress_all.18979035979566644972515112064934558254810760188043142891737377475846460952546
    Line 512, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/32.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 18894011634 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 18894011634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 42.kmac_stress_all.59244603123016474255840351432921228244140601183879609363782134723567206200182
    Line 1095, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/42.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 41081587269 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 41081587269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 3 failures:
- Test kmac_test_vectors_sha3_224 has 2 failures.
  - 2.kmac_test_vectors_sha3_224.97745876008892627154281141632761568110446945082985495521193423570180321402903
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_224/latest/run.log
```
  UVM_ERROR @  49395183 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  49395183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 19.kmac_test_vectors_sha3_224.82648125638667155397791371452623769108009188190945601389287204775625230228930
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_test_vectors_sha3_224/latest/run.log
```
  UVM_ERROR @ 121553551 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 121553551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_sha3_384 has 1 failures.
  - 48.kmac_test_vectors_sha3_384.96135005733551825103264503827903143588784593334974048473219249084535752042206
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/48.kmac_test_vectors_sha3_384/latest/run.log
```
  UVM_ERROR @ 100636771 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 100636771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 3 failures:

Test kmac_app has 3 failures.

11.kmac_app.48362785387183867902067552995367727401605258376079026676459286340497639145641
Line 305, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_app/latest/run.log

  UVM_FATAL @ 3157544327 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (154 [0x9a] vs 121 [0x79]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 3157544327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

22.kmac_app.92407740854551486327188313497080821264888512069485357863082290345900051609990
Line 791, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/22.kmac_app/latest/run.log

  UVM_FATAL @ 142438829431 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (226 [0xe2] vs 203 [0xcb]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 142438829431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 3 failures:
- Test kmac_stress_all_with_rand_reset has 3 failures.
  - 13.kmac_stress_all_with_rand_reset.34938096855399689259710967459687542748332255690077079981087522385043953763059
    Line 1108, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 43700651917 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483744 [0x80000060]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 43700651917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 15.kmac_stress_all_with_rand_reset.108252801673375269173326117315227233647555483986431386576094610814097314334413
    Line 1747, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 25028601916 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483648 [0x80000000]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 25028601916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.