f7fc348358| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | kmac_smoke | 1.586m | 10.350ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | kmac_csr_hw_reset | 1.110s | 28.018us | 5 | 5 | 100.00 |
| V1 | csr_rw | kmac_csr_rw | 1.230s | 99.142us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | kmac_csr_bit_bash | 22.180s | 6.430ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | kmac_csr_aliasing | 10.360s | 1.067ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | kmac_csr_mem_rw_with_rand_reset | 2.710s | 140.703us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | kmac_csr_rw | 1.230s | 99.142us | 20 | 20 | 100.00 |
| kmac_csr_aliasing | 10.360s | 1.067ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | kmac_mem_walk | 0.780s | 11.673us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | kmac_mem_partial_access | 1.650s | 85.883us | 5 | 5 | 100.00 |
| V1 | TOTAL | 115 | 115 | 100.00 | |||
| V2 | long_msg_and_output | kmac_long_msg_and_output | 54.736m | 31.767ms | 50 | 50 | 100.00 |
| V2 | burst_write | kmac_burst_write | 29.639m | 32.883ms | 49 | 50 | 98.00 |
| V2 | test_vectors | kmac_test_vectors_sha3_224 | 42.922m | 404.142ms | 50 | 50 | 100.00 |
| kmac_test_vectors_sha3_256 | 41.316m | 617.190ms | 50 | 50 | 100.00 | ||
| kmac_test_vectors_sha3_384 | 33.741m | 292.610ms | 50 | 50 | 100.00 | ||
| kmac_test_vectors_sha3_512 | 24.154m | 101.738ms | 50 | 50 | 100.00 | ||
| kmac_test_vectors_shake_128 | 1.814h | 1.428s | 50 | 50 | 100.00 | ||
| kmac_test_vectors_shake_256 | 1.594h | 2.196s | 48 | 50 | 96.00 | ||
| kmac_test_vectors_kmac | 8.200s | 4.577ms | 50 | 50 | 100.00 | ||
| kmac_test_vectors_kmac_xof | 7.570s | 673.293us | 50 | 50 | 100.00 | ||
| V2 | sideload | kmac_sideload | 8.671m | 32.830ms | 50 | 50 | 100.00 |
| V2 | app | kmac_app | 7.518m | 59.618ms | 49 | 50 | 98.00 |
| V2 | app_with_partial_data | kmac_app_with_partial_data | 4.891m | 21.341ms | 10 | 10 | 100.00 |
| V2 | entropy_refresh | kmac_entropy_refresh | 7.131m | 18.142ms | 48 | 50 | 96.00 |
| V2 | error | kmac_error | 9.292m | 59.304ms | 48 | 50 | 96.00 |
| V2 | key_error | kmac_key_error | 13.080s | 21.828ms | 49 | 50 | 98.00 |
| V2 | edn_timeout_error | kmac_edn_timeout_error | 45.940s | 4.033ms | 20 | 20 | 100.00 |
| V2 | entropy_mode_error | kmac_entropy_mode_error | 32.600s | 2.387ms | 20 | 20 | 100.00 |
| V2 | entropy_ready_error | kmac_entropy_ready_error | 1.274m | 6.780ms | 10 | 10 | 100.00 |
| V2 | lc_escalation | kmac_lc_escalation | 36.930s | 622.487us | 50 | 50 | 100.00 |
| V2 | stress_all | kmac_stress_all | 50.027m | 428.035ms | 49 | 50 | 98.00 |
| V2 | intr_test | kmac_intr_test | 0.870s | 55.794us | 50 | 50 | 100.00 |
| V2 | alert_test | kmac_alert_test | 0.920s | 16.059us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | kmac_tl_errors | 3.460s | 114.092us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | kmac_tl_errors | 3.460s | 114.092us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | kmac_csr_hw_reset | 1.110s | 28.018us | 5 | 5 | 100.00 |
| kmac_csr_rw | 1.230s | 99.142us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 10.360s | 1.067ms | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 2.660s | 110.834us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | kmac_csr_hw_reset | 1.110s | 28.018us | 5 | 5 | 100.00 |
| kmac_csr_rw | 1.230s | 99.142us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 10.360s | 1.067ms | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 2.660s | 110.834us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1040 | 1050 | 99.05 | |||
| V2S | shadow_reg_update_error | kmac_shadow_reg_errors | 1.530s | 207.437us | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | kmac_shadow_reg_errors | 1.530s | 207.437us | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | kmac_shadow_reg_errors | 1.530s | 207.437us | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | kmac_shadow_reg_errors | 1.530s | 207.437us | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | kmac_shadow_reg_errors_with_csr_rw | 3.610s | 154.281us | 19 | 20 | 95.00 |
| V2S | tl_intg_err | kmac_sec_cm | 1.747m | 30.784ms | 5 | 5 | 100.00 |
| kmac_tl_intg_err | 5.910s | 2.164ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | kmac_tl_intg_err | 5.910s | 2.164ms | 20 | 20 | 100.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | kmac_lc_escalation | 36.930s | 622.487us | 50 | 50 | 100.00 |
| V2S | sec_cm_sw_key_key_masking | kmac_smoke | 1.586m | 10.350ms | 50 | 50 | 100.00 |
| V2S | sec_cm_key_sideload | kmac_sideload | 8.671m | 32.830ms | 50 | 50 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_shadow | kmac_shadow_reg_errors | 1.530s | 207.437us | 20 | 20 | 100.00 |
| V2S | sec_cm_fsm_sparse | kmac_sec_cm | 1.747m | 30.784ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ctr_redun | kmac_sec_cm | 1.747m | 30.784ms | 5 | 5 | 100.00 |
| V2S | sec_cm_packer_ctr_redun | kmac_sec_cm | 1.747m | 30.784ms | 5 | 5 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_regwen | kmac_smoke | 1.586m | 10.350ms | 50 | 50 | 100.00 |
| V2S | sec_cm_fsm_global_esc | kmac_lc_escalation | 36.930s | 622.487us | 50 | 50 | 100.00 |
| V2S | sec_cm_fsm_local_esc | kmac_sec_cm | 1.747m | 30.784ms | 5 | 5 | 100.00 |
| V2S | sec_cm_absorbed_ctrl_mubi | kmac_mubi | 5.341m | 22.572ms | 10 | 10 | 100.00 |
| V2S | sec_cm_sw_cmd_ctrl_sparse | kmac_smoke | 1.586m | 10.350ms | 50 | 50 | 100.00 |
| V2S | TOTAL | 74 | 75 | 98.67 | |||
| V3 | throughput | kmac_throughput | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | kmac_stress_all_with_rand_reset | 1.089h | 274.196ms | 13 | 50 | 26.00 |
| V3 | TOTAL | 13 | 50 | 26.00 | |||
| TOTAL | 1242 | 1290 | 96.28 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 8 | 100.00 |
| V2 | 25 | 25 | 18 | 72.00 |
| V2S | 5 | 5 | 4 | 80.00 |
| V3 | 2 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.10 | 98.10 | 92.66 | 99.89 | 96.36 | 95.91 | 98.89 | 97.89 |
UVM_ERROR (cip_base_vseq.sv:827) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 26 failures:
0.kmac_stress_all_with_rand_reset.5118069968752429397650995742647463306209907997875263763560031083627716855334
Line 912, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 8998601468 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 8998601468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.kmac_stress_all_with_rand_reset.3297412199797984407060399991499635915576988545650567599583729114189486022744
Line 271, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 11067216054 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 11067216054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 24 more failures.
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 8 failures:
8.kmac_stress_all_with_rand_reset.1330991474109127143148315527660997123864557756634357671938564550184815123328
Line 386, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 118738754069 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483672 [0x80000018]) reg name: kmac_reg_block.err_code
UVM_INFO @ 118738754069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.kmac_stress_all_with_rand_reset.93745899299262149393052360952687669298119391051243775698861299035961851955576
Line 975, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 11873732279 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483728 [0x80000050]) reg name: kmac_reg_block.err_code
UVM_INFO @ 11873732279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 5 failures:
Test kmac_stress_all has 1 failures.
9.kmac_stress_all.75364614162799601952005897094370001376433238968824516526233379734616903137000
Line 1224, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_stress_all/latest/run.log
UVM_FATAL @ 35410800495 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 35410800495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_stress_all_with_rand_reset has 2 failures.
18.kmac_stress_all_with_rand_reset.44553618699972557233379756397980750730992523430032698677306932952725703930806
Line 2127, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 104186571469 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 104186571469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
33.kmac_stress_all_with_rand_reset.35800156314814821198132886670971148558448054725362904288381795917097626257649
Line 1335, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/33.kmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 98637579576 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 98637579576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_error has 2 failures.
20.kmac_error.45590456573297005577124664233073002967326414801997496932556030327809467885904
Line 316, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/20.kmac_error/latest/run.log
UVM_FATAL @ 10534904878 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 10534904878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
23.kmac_error.22414560369457102137112093518548230453376791527416538793747218430584498531989
Line 404, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_error/latest/run.log
UVM_FATAL @ 10072274946 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 10072274946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
Test kmac_entropy_refresh has 1 failures.
6.kmac_entropy_refresh.92516966951014221100945058109572344574480955268748553142151574232426657561598
Line 840, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_entropy_refresh/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_burst_write has 1 failures.
14.kmac_burst_write.60027233611333911651583661336923361271417166042413488525097070047042175524696
Line 800, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_burst_write/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_app has 1 failures.
22.kmac_app.36105369956591040172940546597608173978730122049088342484141926794117927160990
Line 767, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/22.kmac_app/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 2 failures:
Test kmac_stress_all_with_rand_reset has 1 failures.
12.kmac_stress_all_with_rand_reset.98972735838697564843503859425697498365164890088529953575698284520103381716892
Line 4875, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 323363676421 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (111 [0x6f] vs 191 [0xbf]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 323363676421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_entropy_refresh has 1 failures.
14.kmac_entropy_refresh.57105194030294776432983445150755366181714450532726018948367209816593870389581
Line 263, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_entropy_refresh/latest/run.log
UVM_FATAL @ 224425016 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (78 [0x4e] vs 100 [0x64]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 224425016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 2 failures:
39.kmac_test_vectors_shake_256.63368497419663717050854807124507632711265941374955488766504895912825992872959
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/39.kmac_test_vectors_shake_256/latest/run.log
UVM_ERROR @ 87799808 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 87799808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
49.kmac_test_vectors_shake_256.16473458699792814425239144131381669763447552604576042145091283178196063024222
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/49.kmac_test_vectors_shake_256/latest/run.log
UVM_ERROR @ 68270875 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 68270875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (kmac_base_vseq.sv:383) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set! has 1 failures:
6.kmac_key_error.43178683171403570959600406966382289115101223718555253681023430338667766852552
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_key_error/latest/run.log
UVM_ERROR @ 67209124 ps: (kmac_base_vseq.sv:383) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
UVM_INFO @ 67209124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.entropy_period reset value: * has 1 failures:
17.kmac_shadow_reg_errors_with_csr_rw.35405042348488681861938306296205620652754557669844050082323142308569183989923
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/17.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
UVM_ERROR @ 24646916 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (278 [0x116] vs 0 [0x0]) Regname: kmac_reg_block.entropy_period reset value: 0x0
UVM_INFO @ 24646916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---