KMAC/MASKED Simulation Results

Thursday March 21 2024 19:02:46 UTC

GitHub Revision: `e3ca274e77`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 110450978848188291656921294920309436568649534904994074551053469482156204817270

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.615m	3.577ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.200s	153.536us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.210s	235.061us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	20.500s	1.450ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.450s	1.592ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.750s	193.264us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.210s	235.061us	20	20	100.00
		kmac_csr_aliasing	10.450s	1.592ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.830s	11.927us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.530s	75.231us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	56.886m	29.470ms	50	50	100.00
V2	burst_write	kmac_burst_write	26.536m	15.491ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	43.764m	404.123ms	49	50	98.00
		kmac_test_vectors_sha3_256	42.988m	647.731ms	48	50	96.00
		kmac_test_vectors_sha3_384	34.251m	284.937ms	49	50	98.00
		kmac_test_vectors_sha3_512	24.932m	565.051ms	49	50	98.00
		kmac_test_vectors_shake_128	1.983h	2.361s	50	50	100.00
		kmac_test_vectors_shake_256	1.710h	2.755s	50	50	100.00
		kmac_test_vectors_kmac	8.720s	5.148ms	49	50	98.00
		kmac_test_vectors_kmac_xof	7.960s	876.363us	50	50	100.00
V2	sideload	kmac_sideload	10.064m	78.003ms	50	50	100.00
V2	app	kmac_app	6.762m	62.260ms	48	50	96.00
V2	app_with_partial_data	kmac_app_with_partial_data	7.068m	59.718ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.235m	68.779ms	48	50	96.00
V2	error	kmac_error	9.501m	200.000ms	47	50	94.00
V2	key_error	kmac_key_error	9.340s	5.790ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	56.890s	9.751ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	30.960s	400.110us	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.004m	23.013ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	1.236m	979.458us	50	50	100.00
V2	stress_all	kmac_stress_all	51.269m	802.715ms	46	50	92.00
V2	intr_test	kmac_intr_test	0.900s	62.911us	50	50	100.00
V2	alert_test	kmac_alert_test	0.960s	128.316us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.270s	71.080us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.270s	71.080us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.200s	153.536us	5	5	100.00
		kmac_csr_rw	1.210s	235.061us	20	20	100.00
		kmac_csr_aliasing	10.450s	1.592ms	5	5	100.00
		kmac_same_csr_outstanding	2.790s	400.574us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.200s	153.536us	5	5	100.00
		kmac_csr_rw	1.210s	235.061us	20	20	100.00
		kmac_csr_aliasing	10.450s	1.592ms	5	5	100.00
		kmac_same_csr_outstanding	2.790s	400.574us	20	20	100.00
V2		TOTAL			1033	1050	98.38
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.380s	116.459us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.380s	116.459us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.380s	116.459us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.380s	116.459us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.000s	389.826us	19	20	95.00
V2S	tl_intg_err	kmac_sec_cm	1.930m	16.039ms	5	5	100.00
		kmac_tl_intg_err	5.690s	1.005ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.690s	1.005ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.236m	979.458us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.615m	3.577ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	10.064m	78.003ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.380s	116.459us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.930m	16.039ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.930m	16.039ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.930m	16.039ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.615m	3.577ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.236m	979.458us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.930m	16.039ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	7.573m	154.650ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.615m	3.577ms	50	50	100.00
V2S		TOTAL			74	75	98.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.027h	285.038ms	15	50	30.00
V3		TOTAL			15	50	30.00
		TOTAL			1237	1290	95.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	16	64.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.10	98.10	92.66	99.89	96.36	95.91	98.89	97.89

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 26 failures:
- Test kmac_stress_all_with_rand_reset has 26 failures.
  - 1.kmac_stress_all_with_rand_reset.11343265495556039067937834361583777008594433366576780145518160265253207825550
    Line 534, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7035555555 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 7035555555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.kmac_stress_all_with_rand_reset.14434476354318221659083957416504232237379509319453046209326119198889081142337
    Line 347, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1685328031 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1685328031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 24 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 7 failures:

Test kmac_test_vectors_sha3_384 has 1 failures.

6.kmac_test_vectors_sha3_384.45136741063553006146936956948496491316482136293671341458256053989388594437473
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_test_vectors_sha3_384/latest/run.log

  UVM_ERROR @ 420565390 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 420565390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_test_vectors_sha3_256 has 2 failures.

12.kmac_test_vectors_sha3_256.54287299680439572311177986778360590663613386409762750341218866958678107033529
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_test_vectors_sha3_256/latest/run.log

  UVM_ERROR @  82373072 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  82373072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

49.kmac_test_vectors_sha3_256.111574239883890362854043572303146238758151038210662961230445615187359249543581
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/49.kmac_test_vectors_sha3_256/latest/run.log

  UVM_ERROR @  21585559 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  21585559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_test_vectors_kmac has 1 failures.

13.kmac_test_vectors_kmac.71846381206795072233599261400618912745070565359981466445557141069561930890771
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_test_vectors_kmac/latest/run.log

  UVM_ERROR @ 215128037 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 215128037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_test_vectors_sha3_224 has 1 failures.

22.kmac_test_vectors_sha3_224.42723291743112303596660616789596020335397233043713407152772511614673108351778
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/22.kmac_test_vectors_sha3_224/latest/run.log

  UVM_ERROR @  56789944 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  56789944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 1 failures.

40.kmac_stress_all.34084028424742495386688183993633634166271742432745550851065229626838280669539
Line 681, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/40.kmac_stress_all/latest/run.log

  UVM_ERROR @ 20081046229 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 20081046229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more tests.

UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 7 failures:
- Test kmac_error has 2 failures.
  - 19.kmac_error.12810342534352286314325241363140497132286128298477889623442225179239054775203
    Line 651, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_error/latest/run.log
```
  UVM_FATAL @ 10072566843 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 10072566843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 45.kmac_error.93612736725271111789168150210259024482419479078447970930028522264450349064034
    Line 782, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/45.kmac_error/latest/run.log
```
  UVM_FATAL @ 10079720574 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 10079720574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_stress_all has 2 failures.
  - 19.kmac_stress_all.115540024730947948792416450629921419196681074343470242058426626080421043311804
    Line 1490, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 71867111581 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 71867111581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 23.kmac_stress_all.44783679747070702034767849089303905645225618452132959573307605668102282972138
    Line 403, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 11735772575 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 11735772575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_stress_all_with_rand_reset has 3 failures.
  - 20.kmac_stress_all_with_rand_reset.5843019318927989062402682117424290302589605208664141309008515373097936675085
    Line 589, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/20.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 19703423024 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 19703423024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 37.kmac_stress_all_with_rand_reset.85693615040422837426797615243003810069485255057778489039073400017079611607516
    Line 1708, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/37.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 145106392925 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 145106392925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 6 failures:
- Test kmac_stress_all_with_rand_reset has 6 failures.
  - 3.kmac_stress_all_with_rand_reset.29469552923802112267423870513718619278338354171719328185472244516063616149255
    Line 765, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 61855684867 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483664 [0x80000010]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 61855684867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 13.kmac_stress_all_with_rand_reset.3238173979231424479159332033986988903889215702298374428768925658086619749655
    Line 2031, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 184261307953 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483768 [0x80000078]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 184261307953 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 3 failures:

Test kmac_stress_all has 1 failures.

7.kmac_stress_all.10570992235077824699931884773175197271792951446160091198617592200374601337801
Line 513, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_stress_all/latest/run.log

  UVM_FATAL @ 17818775867 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (184 [0xb8] vs 104 [0x68]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 17818775867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 1 failures.

14.kmac_entropy_refresh.26521713000337980316751366413197337595530957914598231453061751666422163769488
Line 535, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 5099769301 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (35 [0x23] vs 189 [0xbd]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 5099769301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 1 failures.

23.kmac_app.108504467138141571073545557286670646847241245245329581129281141102849837395462
Line 319, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_app/latest/run.log

  UVM_FATAL @ 507255236 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (19 [0x13] vs 30 [0x1e]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 507255236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
- Test kmac_entropy_refresh has 1 failures.
  - 25.kmac_entropy_refresh.64597251271613202762211349638754114755628766476917743324280135819007968013938
    Line 938, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/25.kmac_entropy_refresh/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_error has 1 failures.
  - 38.kmac_error.21568672935275473491505466430366835556730046321595581970360887292439180970997
    Line 1262, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/38.kmac_error/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_app has 1 failures.
  - 45.kmac_app.83700570948939562646715865795794672269663938692742534206408301793713424078891
    Line 986, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/45.kmac_app/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_*.prefix_* reset value: * has 1 failures:
- Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.
  - 8.kmac_shadow_reg_errors_with_csr_rw.42156500453671831511396125967259563228370948928503421832873789219899966932181
    Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @  21044708 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (3553740907 [0xd3d1c86b] vs 0 [0x0]) Regname: kmac_reg_block.prefix_3.prefix_0 reset value: 0x0
  UVM_INFO @  21044708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```