KMAC/MASKED Simulation Results

Sunday March 24 2024 19:02:40 UTC

GitHub Revision: `70ad420931`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 56687816123908180356912499273064417112757374299033127319246303583078997854118

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.540m	17.864ms	49	50	98.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.180s	98.844us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.290s	101.329us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	21.860s	8.479ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	8.070s	149.189us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.540s	340.724us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.290s	101.329us	20	20	100.00
		kmac_csr_aliasing	8.070s	149.189us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.770s	32.086us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.390s	70.350us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	long_msg_and_output	kmac_long_msg_and_output	51.525m	81.910ms	50	50	100.00
V2	burst_write	kmac_burst_write	28.497m	18.854ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	44.232m	391.276ms	50	50	100.00
		kmac_test_vectors_sha3_256	41.670m	1.549s	48	50	96.00
		kmac_test_vectors_sha3_384	31.185m	72.448ms	50	50	100.00
		kmac_test_vectors_sha3_512	23.805m	642.199ms	50	50	100.00
		kmac_test_vectors_shake_128	1.849h	1.080s	50	50	100.00
		kmac_test_vectors_shake_256	1.720h	2.411s	50	50	100.00
		kmac_test_vectors_kmac	8.420s	4.343ms	50	50	100.00
		kmac_test_vectors_kmac_xof	7.470s	1.024ms	50	50	100.00
V2	sideload	kmac_sideload	9.301m	23.515ms	49	50	98.00
V2	app	kmac_app	7.115m	60.802ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.421m	21.992ms	9	10	90.00
V2	entropy_refresh	kmac_entropy_refresh	6.830m	27.799ms	48	50	96.00
V2	error	kmac_error	8.505m	57.279ms	50	50	100.00
V2	key_error	kmac_key_error	6.960s	15.187ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	46.390s	1.026ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	51.720s	6.955ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.273m	26.006ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	41.480s	1.134ms	50	50	100.00
V2	stress_all	kmac_stress_all	52.912m	116.250ms	47	50	94.00
V2	intr_test	kmac_intr_test	0.880s	14.900us	50	50	100.00
V2	alert_test	kmac_alert_test	0.960s	20.342us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.520s	152.701us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.520s	152.701us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.180s	98.844us	5	5	100.00
		kmac_csr_rw	1.290s	101.329us	20	20	100.00
		kmac_csr_aliasing	8.070s	149.189us	5	5	100.00
		kmac_same_csr_outstanding	2.860s	487.535us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.180s	98.844us	5	5	100.00
		kmac_csr_rw	1.290s	101.329us	20	20	100.00
		kmac_csr_aliasing	8.070s	149.189us	5	5	100.00
		kmac_same_csr_outstanding	2.860s	487.535us	20	20	100.00
V2		TOTAL			1040	1050	99.05
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.420s	594.755us	19	20	95.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.420s	594.755us	19	20	95.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.420s	594.755us	19	20	95.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.420s	594.755us	19	20	95.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.260s	1.241ms	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.978m	27.913ms	5	5	100.00
		kmac_tl_intg_err	4.980s	926.547us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.980s	926.547us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	41.480s	1.134ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.540m	17.864ms	49	50	98.00
V2S	sec_cm_key_sideload	kmac_sideload	9.301m	23.515ms	49	50	98.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.420s	594.755us	19	20	95.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.978m	27.913ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.978m	27.913ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.978m	27.913ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.540m	17.864ms	49	50	98.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	41.480s	1.134ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.978m	27.913ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	7.355m	37.118ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.540m	17.864ms	49	50	98.00
V2S		TOTAL			74	75	98.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	38.297m	47.965ms	15	50	30.00
V3		TOTAL			15	50	30.00
		TOTAL			1243	1290	96.36

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	25	25	19	76.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.95	98.10	92.66	99.89	95.45	95.91	98.89	97.75

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 26 failures:
- Test kmac_stress_all_with_rand_reset has 26 failures.
  - 0.kmac_stress_all_with_rand_reset.44201545463089973656475748301990754524215341733356453456845082625944509387982
    Line 1183, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 198087959681 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 198087959681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.69054132863083493143809300216832914048783449619806738598764708423455572446108
    Line 1172, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 44816620555 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 44816620555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 24 more failures.
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 9 failures:
- Test kmac_stress_all_with_rand_reset has 9 failures.
  - 2.kmac_stress_all_with_rand_reset.47983338905222397006975007471029197435853067839437806534650359227433263421844
    Line 516, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 243948722261 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483648 [0x80000000]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 243948722261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 15.kmac_stress_all_with_rand_reset.79127132426382036195793402493156064975774439772134424039873592517976516568056
    Line 2028, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 26193542871 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483664 [0x80000010]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 26193542871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
- Test kmac_burst_write has 1 failures.
  - 6.kmac_burst_write.110192053522143885035759334602125856190663057541438149047686462266459393967170
    Line 986, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_app_with_partial_data has 1 failures.
  - 7.kmac_app_with_partial_data.103012437887837390768076530872124891208089733209323843943676199946358853929980
    Line 672, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_app_with_partial_data/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_sideload has 1 failures.
  - 44.kmac_sideload.42113593496623441017546679605968767335303669044654481144168921605178739648876
    Line 891, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/44.kmac_sideload/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 3 failures:
- Test kmac_test_vectors_sha3_256 has 2 failures.
  - 24.kmac_test_vectors_sha3_256.113408431245074816200016828106907432210254928532060628083493841864543929651123
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/24.kmac_test_vectors_sha3_256/latest/run.log
```
  UVM_ERROR @  85018967 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  85018967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 26.kmac_test_vectors_sha3_256.63993013351162143253758887143822075422827657123526190406971750778093348534995
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/26.kmac_test_vectors_sha3_256/latest/run.log
```
  UVM_ERROR @  56763825 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  56763825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_smoke has 1 failures.
  - 44.kmac_smoke.61278593416847955072097223007015596597139263120994960570147579003482043881960
    Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/44.kmac_smoke/latest/run.log
```
  UVM_ERROR @ 132836247 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 132836247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 3 failures:

Test kmac_entropy_refresh has 2 failures.

36.kmac_entropy_refresh.28289489961594959303204905351459751143367342205381714884380094569037065797707
Line 263, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/36.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 349508240 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (82 [0x52] vs 52 [0x34]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 349508240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

45.kmac_entropy_refresh.72445389484768713005340460748098911321841572196697332251790066615915243749545
Line 297, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/45.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 1821009763 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (248 [0xf8] vs 22 [0x16]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 1821009763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 1 failures.

37.kmac_stress_all.31205875256014625612437192260869387284247302546495786601748089397266831469224
Line 729, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/37.kmac_stress_all/latest/run.log

  UVM_FATAL @ 6326247083 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (96 [0x60] vs 93 [0x5d]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 6326247083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 2 failures:
- Test kmac_stress_all has 2 failures.
  - 14.kmac_stress_all.58383005540445167306542266884610201139042833571212903521709211071481381024402
    Line 1000, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 86987727960 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 86987727960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 36.kmac_stress_all.96067973366172000457940216746320334244269142798960978715751175417721098278219
    Line 1734, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/36.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 84142985155 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 84142985155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:

Test kmac_shadow_reg_errors has 1 failures.

12.kmac_shadow_reg_errors.105566173347056502979699413805207569907081589822331965272157909199148967994217
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_shadow_reg_errors/latest/run.log

  [make]: simulate
  cd /workspace/12.kmac_shadow_reg_errors/latest && /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678530921 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg_errors.2678530921 +enable_masking=1 +sw_key_masked=0
  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Mar 24 12:36 2024
  Cannot find license file.
  Make sure that you have a license file and that your
  LM_LICENSE_FILE is pointing to the right location.
  
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255