KMAC/MASKED Simulation Results

Sunday May 12 2024 19:02:35 UTC

GitHub Revision: `69c572b503`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 72674276607041733394622960695970595070180537542023880499199659375034056632550

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.627m	11.843ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.190s	41.675us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.300s	42.764us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	21.240s	1.646ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.080s	1.565ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.650s	740.469us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.300s	42.764us	20	20	100.00
		kmac_csr_aliasing	10.080s	1.565ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.790s	38.511us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.560s	72.377us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	55.782m	255.674ms	50	50	100.00
V2	burst_write	kmac_burst_write	29.505m	36.977ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	43.519m	670.392ms	50	50	100.00
		kmac_test_vectors_sha3_256	51.031m	1.854s	50	50	100.00
		kmac_test_vectors_sha3_384	31.564m	189.684ms	50	50	100.00
		kmac_test_vectors_sha3_512	25.329m	201.059ms	49	50	98.00
		kmac_test_vectors_shake_128	1.970h	1.775s	50	50	100.00
		kmac_test_vectors_shake_256	1.656h	1.378s	49	50	98.00
		kmac_test_vectors_kmac	7.840s	497.157us	50	50	100.00
		kmac_test_vectors_kmac_xof	7.190s	501.248us	50	50	100.00
V2	sideload	kmac_sideload	8.664m	21.293ms	50	50	100.00
V2	app	kmac_app	6.557m	15.055ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.212m	39.329ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.573m	69.373ms	50	50	100.00
V2	error	kmac_error	8.791m	18.947ms	50	50	100.00
V2	key_error	kmac_key_error	14.250s	3.255ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	56.810s	1.618ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	38.360s	436.316us	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.160m	5.982ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	31.860s	884.400us	50	50	100.00
V2	stress_all	kmac_stress_all	51.046m	857.920ms	47	50	94.00
V2	intr_test	kmac_intr_test	0.890s	30.033us	50	50	100.00
V2	alert_test	kmac_alert_test	0.910s	223.899us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.660s	119.969us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.660s	119.969us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.190s	41.675us	5	5	100.00
		kmac_csr_rw	1.300s	42.764us	20	20	100.00
		kmac_csr_aliasing	10.080s	1.565ms	5	5	100.00
		kmac_same_csr_outstanding	2.670s	290.502us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.190s	41.675us	5	5	100.00
		kmac_csr_rw	1.300s	42.764us	20	20	100.00
		kmac_csr_aliasing	10.080s	1.565ms	5	5	100.00
		kmac_same_csr_outstanding	2.670s	290.502us	20	20	100.00
V2		TOTAL			1044	1050	99.43
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.480s	74.554us	19	20	95.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.480s	74.554us	19	20	95.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.480s	74.554us	19	20	95.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.480s	74.554us	19	20	95.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.090s	934.239us	15	20	75.00
V2S	tl_intg_err	kmac_sec_cm	1.605m	7.138ms	5	5	100.00
		kmac_tl_intg_err	4.940s	311.326us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.940s	311.326us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	31.860s	884.400us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.627m	11.843ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	8.664m	21.293ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.480s	74.554us	19	20	95.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.605m	7.138ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.605m	7.138ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.605m	7.138ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.627m	11.843ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	31.860s	884.400us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.605m	7.138ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.071m	24.666ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.627m	11.843ms	50	50	100.00
V2S		TOTAL			69	75	92.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.034h	216.449ms	19	50	38.00
V3		TOTAL			19	50	38.00
		TOTAL			1247	1290	96.67

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	21	84.00
V2S	5	5	3	60.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.35	97.91	92.64	99.89	77.46	95.59	99.04	97.88

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:
- Test kmac_stress_all_with_rand_reset has 24 failures.
  - 5.kmac_stress_all_with_rand_reset.83388547376704914329377064907285592737725880126887551849638648743049351260484
    Line 407, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2770530641 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2770530641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.kmac_stress_all_with_rand_reset.19490035538900767050292896386211463820480338824112300392517496613058311066076
    Line 297, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1005248280 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1005248280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 22 more failures.
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 7 failures:
- Test kmac_stress_all_with_rand_reset has 7 failures.
  - 10.kmac_stress_all_with_rand_reset.45352138530292492725200454350115896657953104314389379844770953584534195171885
    Line 1914, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 67773624513 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483664 [0x80000010]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 67773624513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 15.kmac_stress_all_with_rand_reset.90995138529289227435843504095008061894564245600015623728557031630254316608599
    Line 338, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 447664535 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483656 [0x80000008]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 447664535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 6 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 5 failures.

2.kmac_shadow_reg_errors_with_csr_rw.37351378394608352040777255684192131175685792135976954976323269401727040107622
Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @ 174561530 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @ 174561530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.kmac_shadow_reg_errors_with_csr_rw.12843470888299196473988901994976406520605383162002679545169273435149289803992
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  12363849 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  12363849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test kmac_shadow_reg_errors has 1 failures.

18.kmac_shadow_reg_errors.57476774193700562040383256611106095993768459886610699732255967609176265844171
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @   3820734 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @   3820734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 3 failures:
- Test kmac_test_vectors_shake_256 has 1 failures.
  - 9.kmac_test_vectors_shake_256.38962650152997628325440633063745555489009717261186766695301527741493742132655
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_test_vectors_shake_256/latest/run.log
```
  UVM_ERROR @  38055735 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  38055735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_stress_all has 1 failures.
  - 30.kmac_stress_all.96377407674618679336023001131460871393507430952648326718273653891426668022150
    Line 921, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/30.kmac_stress_all/latest/run.log
```
  UVM_ERROR @ 14480703433 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 14480703433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_sha3_512 has 1 failures.
  - 44.kmac_test_vectors_sha3_512.47004424551952556075947442086877181087149071265635344190171400980921503953711
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/44.kmac_test_vectors_sha3_512/latest/run.log
```
  UVM_ERROR @  22113674 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  22113674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 2 failures:
- Test kmac_stress_all has 2 failures.
  - 0.kmac_stress_all.46656707016750265466119574517746327269489050485887833366851800545700601198838
    Line 1314, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 16250242525 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 16250242525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 11.kmac_stress_all.69036785157294210713671949747976290165534798001318136453590053805250646194695
    Line 2168, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 41646068169 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 41646068169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_burst_write has 1 failures.
  - 42.kmac_burst_write.115469589023510798802787647444816276859761244648282474547933048665282668301347
    Line 723, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/42.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```