KMAC/MASKED Simulation Results

Tuesday May 14 2024 19:02:33 UTC

GitHub Revision: `00fe426038`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 56275124637035941820967954627144971699378360917446801543187025394370981034792

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.523m	4.458ms	49	50	98.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.100s	60.813us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.290s	39.314us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	18.640s	3.847ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.550s	547.082us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.720s	43.649us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.290s	39.314us	20	20	100.00
		kmac_csr_aliasing	9.550s	547.082us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.810s	17.682us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.500s	39.179us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	long_msg_and_output	kmac_long_msg_and_output	59.056m	95.413ms	50	50	100.00
V2	burst_write	kmac_burst_write	24.239m	51.282ms	47	50	94.00
V2	test_vectors	kmac_test_vectors_sha3_224	42.913m	454.940ms	50	50	100.00
		kmac_test_vectors_sha3_256	40.202m	191.518ms	50	50	100.00
		kmac_test_vectors_sha3_384	33.085m	334.307ms	50	50	100.00
		kmac_test_vectors_sha3_512	23.981m	142.534ms	50	50	100.00
		kmac_test_vectors_shake_128	1.961h	3.777s	49	50	98.00
		kmac_test_vectors_shake_256	1.633h	416.328ms	49	50	98.00
		kmac_test_vectors_kmac	7.920s	3.615ms	50	50	100.00
		kmac_test_vectors_kmac_xof	7.320s	206.171us	50	50	100.00
V2	sideload	kmac_sideload	8.292m	5.586ms	50	50	100.00
V2	app	kmac_app	7.450m	14.078ms	46	50	92.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.170m	6.155ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.168m	31.623ms	48	50	96.00
V2	error	kmac_error	8.276m	59.201ms	50	50	100.00
V2	key_error	kmac_key_error	16.810s	16.538ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	51.480s	2.411ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	41.010s	3.274ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.212m	6.969ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	49.170s	813.492us	50	50	100.00
V2	stress_all	kmac_stress_all	49.681m	258.658ms	45	50	90.00
V2	intr_test	kmac_intr_test	0.880s	25.243us	50	50	100.00
V2	alert_test	kmac_alert_test	0.980s	24.985us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.220s	135.142us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.220s	135.142us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.100s	60.813us	5	5	100.00
		kmac_csr_rw	1.290s	39.314us	20	20	100.00
		kmac_csr_aliasing	9.550s	547.082us	5	5	100.00
		kmac_same_csr_outstanding	2.860s	1.045ms	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.100s	60.813us	5	5	100.00
		kmac_csr_rw	1.290s	39.314us	20	20	100.00
		kmac_csr_aliasing	9.550s	547.082us	5	5	100.00
		kmac_same_csr_outstanding	2.860s	1.045ms	20	20	100.00
V2		TOTAL			1034	1050	98.48
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.550s	96.596us	15	20	75.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.550s	96.596us	15	20	75.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.550s	96.596us	15	20	75.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.550s	96.596us	15	20	75.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.160s	450.864us	18	20	90.00
V2S	tl_intg_err	kmac_sec_cm	1.971m	32.876ms	5	5	100.00
		kmac_tl_intg_err	5.140s	983.139us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.140s	983.139us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	49.170s	813.492us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.523m	4.458ms	49	50	98.00
V2S	sec_cm_key_sideload	kmac_sideload	8.292m	5.586ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.550s	96.596us	15	20	75.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.971m	32.876ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.971m	32.876ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.971m	32.876ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.523m	4.458ms	49	50	98.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	49.170s	813.492us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.971m	32.876ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.573m	24.744ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.523m	4.458ms	49	50	98.00
V2S		TOTAL			68	75	90.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.070h	694.602ms	11	50	22.00
V3		TOTAL			11	50	22.00
		TOTAL			1227	1290	95.12

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	25	25	19	76.00
V2S	5	5	3	60.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.20	97.89	92.58	99.89	76.76	95.53	98.88	97.88

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 27 failures:
- Test kmac_stress_all_with_rand_reset has 27 failures.
  - 0.kmac_stress_all_with_rand_reset.69221196434295585518902325753118480833175697141410577448370761506944745789554
    Line 405, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2917743497 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2917743497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.62486590688186938269472504000684952224104111273406630500734838314885357584986
    Line 403, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8877508822 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 8877508822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 25 more failures.
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 8 failures:
- Test kmac_stress_all_with_rand_reset has 8 failures.
  - 4.kmac_stress_all_with_rand_reset.71561881809601746868324359343002703420401538998001263262844080393185765147633
    Line 260, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  60598323 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483672 [0x80000018]) reg name: kmac_reg_block.err_code
  UVM_INFO @  60598323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 11.kmac_stress_all_with_rand_reset.44864556543846833157829368549957465251783204507200055219061146104331150308234
    Line 620, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 53590793293 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483672 [0x80000018]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 53590793293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 7 failures:

Test kmac_shadow_reg_errors has 5 failures.

0.kmac_shadow_reg_errors.29038345408998497155622666421214859526891947229963323067111166987149010659085
Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  88583771 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  88583771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.kmac_shadow_reg_errors.42119895318505529409471433814211265445416039826866953208961833720736010406653
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  11856749 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  11856749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test kmac_shadow_reg_errors_with_csr_rw has 2 failures.

3.kmac_shadow_reg_errors_with_csr_rw.72513745789213638840205627712999963974817902392501080051487226184832166635357
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  20987042 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  20987042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.kmac_shadow_reg_errors_with_csr_rw.10878272281306050319784123831206763991466765587290738804960364466541842208169
Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @ 227917823 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @ 227917823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 7 failures:
- Test kmac_stress_all has 4 failures.
  - 4.kmac_stress_all.106966630251792912930923154706925793983797636016639461125398904975408204098202
    Line 988, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 65390622834 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 65390622834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 43.kmac_stress_all.61270623752450319975044843910354956003440739464727904116038366660007419815616
    Line 1018, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/43.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 28113039712 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 28113039712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
- Test kmac_stress_all_with_rand_reset has 3 failures.
  - 19.kmac_stress_all_with_rand_reset.107386933458539140453986782801749796076435368972687992923541745935967342923527
    Line 636, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 48093723772 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 48093723772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 23.kmac_stress_all_with_rand_reset.34775314004841784030343621616894888793715264459041131905444650298940026229767
    Line 1396, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 158638386653 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 158638386653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 6 failures:

Test kmac_app has 3 failures.

2.kmac_app.59943929250812387752307021192538326345619577101804673521504341198344919379026
Line 313, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_app/latest/run.log

  UVM_FATAL @ 1499785031 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (142 [0x8e] vs 193 [0xc1]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 1499785031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

14.kmac_app.46751541921940340354371809646487346202187117099621827526102571729747405208225
Line 419, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_app/latest/run.log

  UVM_FATAL @ 12667517540 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (131 [0x83] vs 39 [0x27]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 12667517540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test kmac_entropy_refresh has 2 failures.

6.kmac_entropy_refresh.109308154727312452056062896479484645383018525627556950061373165949337553720819
Line 705, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 10144472515 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (245 [0xf5] vs 131 [0x83]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 10144472515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

48.kmac_entropy_refresh.82379950927427000293154707513326626481275204980620385565619413249809976337037
Line 369, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/48.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 4961015282 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (111 [0x6f] vs 2 [0x2]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 4961015282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all_with_rand_reset has 1 failures.

43.kmac_stress_all_with_rand_reset.43593519695587800228894522151386471175954535322277955651930574493873604979243
Line 929, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/43.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 105837383443 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (47 [0x2f] vs 95 [0x5f]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 105837383443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
- Test kmac_burst_write has 3 failures.
  - 3.kmac_burst_write.79274314259884504795403282922612930492102020814929302650873739795066592201438
    Line 1058, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.kmac_burst_write.102226766902448866370144640479277761449153072895656442738181023736996225378525
    Line 1022, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test kmac_app has 1 failures.
  - 19.kmac_app.82133723801457622000649092266309540601808047601415789043729339465021267163587
    Line 984, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_app/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 2 failures:
- Test kmac_test_vectors_shake_256 has 1 failures.
  - 23.kmac_test_vectors_shake_256.70107000554433776190125700742368080204767637959762603327058768318080534527510
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_test_vectors_shake_256/latest/run.log
```
  UVM_ERROR @ 220935225 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 220935225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_stress_all has 1 failures.
  - 36.kmac_stress_all.38673479217894419580863019727887145073677698099057388189758582185999364112723
    Line 643, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/36.kmac_stress_all/latest/run.log
```
  UVM_ERROR @ 9113246831 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 9113246831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test kmac_test_vectors_shake_128 has 1 failures.
  - 40.kmac_test_vectors_shake_128.73839796060668636491761300318246854512031224695137501075975945023096862656542
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/40.kmac_test_vectors_shake_128/latest/run.log
```
  Job ID: smart:59425a0b-a89e-4ae5-b88d-64bf87b40aea
```
Offending '(rand_valid_o || $past(seed_done))' has 1 failures:
- Test kmac_smoke has 1 failures.
  - 41.kmac_smoke.100366214963296657235988026579344171373327150354891469870153188884459938992313
    Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/41.kmac_smoke/latest/run.log
```
      Offending '(rand_valid_o || $past(seed_done))'
  UVM_ERROR @  10505464 ps: (kmac_entropy.sv:457) [ASSERT FAILED] ConsumeNotAssertWhenNotValid_M
  UVM_INFO @  10505464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```