KMAC/MASKED Simulation Results

Thursday May 16 2024 19:02:11 UTC

GitHub Revision: `349bab6601`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 60729333463373082946889975499553948547086354767408862399987151421185145065082

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.632m	20.268ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.160s	29.023us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.260s	34.709us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	23.900s	3.012ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.220s	766.974us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.860s	137.141us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.260s	34.709us	20	20	100.00
		kmac_csr_aliasing	9.220s	766.974us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.800s	20.885us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.500s	147.212us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	50.988m	103.627ms	50	50	100.00
V2	burst_write	kmac_burst_write	25.670m	159.506ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	46.682m	1.377s	50	50	100.00
		kmac_test_vectors_sha3_256	38.476m	109.905ms	50	50	100.00
		kmac_test_vectors_sha3_384	32.018m	296.132ms	50	50	100.00
		kmac_test_vectors_sha3_512	23.325m	191.124ms	50	50	100.00
		kmac_test_vectors_shake_128	1.830h	2.187s	50	50	100.00
		kmac_test_vectors_shake_256	1.557h	353.296ms	50	50	100.00
		kmac_test_vectors_kmac	7.120s	481.777us	50	50	100.00
		kmac_test_vectors_kmac_xof	7.150s	320.992us	50	50	100.00
V2	sideload	kmac_sideload	8.536m	70.185ms	50	50	100.00
V2	app	kmac_app	7.024m	5.755ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	7.387m	12.952ms	9	10	90.00
V2	entropy_refresh	kmac_entropy_refresh	6.960m	34.987ms	49	50	98.00
V2	error	kmac_error	8.173m	14.334ms	47	50	94.00
V2	key_error	kmac_key_error	15.310s	6.398ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	49.530s	1.279ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	33.180s	2.140ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.209m	25.766ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	52.430s	4.059ms	50	50	100.00
V2	stress_all	kmac_stress_all	1.131h	1.507s	48	50	96.00
V2	intr_test	kmac_intr_test	0.890s	15.041us	50	50	100.00
V2	alert_test	kmac_alert_test	0.930s	146.592us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.580s	126.675us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.580s	126.675us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.160s	29.023us	5	5	100.00
		kmac_csr_rw	1.260s	34.709us	20	20	100.00
		kmac_csr_aliasing	9.220s	766.974us	5	5	100.00
		kmac_same_csr_outstanding	2.790s	560.569us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.160s	29.023us	5	5	100.00
		kmac_csr_rw	1.260s	34.709us	20	20	100.00
		kmac_csr_aliasing	9.220s	766.974us	5	5	100.00
		kmac_same_csr_outstanding	2.790s	560.569us	20	20	100.00
V2		TOTAL			1041	1050	99.14
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.670s	78.826us	18	20	90.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.670s	78.826us	18	20	90.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.670s	78.826us	18	20	90.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.670s	78.826us	18	20	90.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.080s	1.297ms	18	20	90.00
V2S	tl_intg_err	kmac_sec_cm	1.705m	7.403ms	5	5	100.00
		kmac_tl_intg_err	5.460s	920.781us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.460s	920.781us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	52.430s	4.059ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.632m	20.268ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	8.536m	70.185ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.670s	78.826us	18	20	90.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.705m	7.403ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.705m	7.403ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.705m	7.403ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.632m	20.268ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	52.430s	4.059ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.705m	7.403ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.499m	38.454ms	9	10	90.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.632m	20.268ms	50	50	100.00
V2S		TOTAL			70	75	93.33
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.157h	78.563ms	15	50	30.00
V3		TOTAL			15	50	30.00
		TOTAL			1241	1290	96.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	19	76.00
V2S	5	5	2	40.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.20	97.89	92.55	99.89	76.76	95.53	98.88	97.88

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 27 failures:
- Test kmac_stress_all_with_rand_reset has 27 failures.
  - 3.kmac_stress_all_with_rand_reset.99279079413522645236394031830480947181210701949968086894289066726110620509896
    Line 388, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 47861254887 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 47861254887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.kmac_stress_all_with_rand_reset.27514925270958762924967510327231763187707979489427093323049669284327823749740
    Line 361, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6280586331 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 6280586331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 25 more failures.
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 6 failures:
- Test kmac_stress_all_with_rand_reset has 6 failures.
  - 1.kmac_stress_all_with_rand_reset.42986377282207797216490659079840808772847390826939959221935058698252996273500
    Line 281, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 541829136 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483664 [0x80000010]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 541829136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.kmac_stress_all_with_rand_reset.98428718773759865135967338589947501417266447499416683224472878806867754502970
    Line 797, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 19801296510 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483760 [0x80000070]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 19801296510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 4 failures:

Test kmac_stress_all_with_rand_reset has 1 failures.

0.kmac_stress_all_with_rand_reset.54007622736025437115816699300768742908497205887566403100506179290650069060407
Line 1554, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 264071429344 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (227 [0xe3] vs 164 [0xa4]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 264071429344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app_with_partial_data has 1 failures.

2.kmac_app_with_partial_data.8296464071248765131653470547621485008246996038638013875406907858597622658883
Line 845, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_app_with_partial_data/latest/run.log

  UVM_FATAL @ 78019303428 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (191 [0xbf] vs 167 [0xa7]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 78019303428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 1 failures.

23.kmac_app.23082956958393555997089336521274436809109742379746389076425175028855833772466
Line 501, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_app/latest/run.log

  UVM_FATAL @ 7552048759 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (86 [0x56] vs 79 [0x4f]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 7552048759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 1 failures.

40.kmac_entropy_refresh.59737505397897097252800921782234548854407797425474883833134546222074050025957
Line 1001, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/40.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 8655808795 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (233 [0xe9] vs 175 [0xaf]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 8655808795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 4 failures:

Test kmac_shadow_reg_errors has 2 failures.

0.kmac_shadow_reg_errors.16113975257405276667329492955734343120181217220547928524505439723880253621452
Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  38935703 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  38935703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

19.kmac_shadow_reg_errors.68246699748216850168609404077049512614876595397466627852167639506559518810611
Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  57489824 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  57489824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_shadow_reg_errors_with_csr_rw has 2 failures.

7.kmac_shadow_reg_errors_with_csr_rw.77797410267430242745579368297657628451798814480076222829025169642259993021920
Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @ 102129876 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @ 102129876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

11.kmac_shadow_reg_errors_with_csr_rw.112989131449993053714307055257585327635126993016517109681846603523584360073421
Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @ 214545131 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @ 214545131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 4 failures:
- Test kmac_error has 3 failures.
  - 8.kmac_error.66870929913309787120470157706990389077285864201466452088991755600205049325736
    Line 395, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_error/latest/run.log
```
  UVM_FATAL @ 10403949189 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 10403949189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 23.kmac_error.97495792558245728703968490373682196241249238358412826475296661415562738544338
    Line 755, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_error/latest/run.log
```
  UVM_FATAL @ 10035500065 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 10035500065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 31.kmac_stress_all_with_rand_reset.57246759412444611239280884389411534660002402903194939576871473115487257936705
    Line 1717, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/31.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 24156455740 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 24156455740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 2 failures:
- Test kmac_stress_all has 2 failures.
  - 15.kmac_stress_all.5203022452600961791689179484607324708172842784675065355365768757884710308003
    Line 677, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_stress_all/latest/run.log
```
  UVM_ERROR @ 6506455057 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 6506455057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 21.kmac_stress_all.20858345654696164753552998724103096601879983300032048779438474392794174042791
    Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/21.kmac_stress_all/latest/run.log
```
  UVM_ERROR @  64040919 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  64040919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_burst_write has 1 failures.
  - 2.kmac_burst_write.28279848713202912284986921097074368199320128944186592338873883025743384309720
    Line 848, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (kmac_scoreboard.sv:1339) [scoreboard] Check failed digest_share*.size() == output_len_bytes (* [*] vs * [*]) Calculated output length(32) doesn't match actual output length(48)! has 1 failures:
- Test kmac_mubi has 1 failures.
  - 6.kmac_mubi.43178343355840685378209175640106501609747890328632972675678256185301735154068
    Line 351, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_mubi/latest/run.log
```
  UVM_FATAL @ 1557454785 ps: (kmac_scoreboard.sv:1339) [uvm_test_top.env.scoreboard] Check failed digest_share0.size() == output_len_bytes (48 [0x30] vs 32 [0x20]) Calculated output length(32) doesn't match actual output length(48)!
  UVM_INFO @ 1557454785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```