KMAC/MASKED Simulation Results

Sunday May 19 2024 19:02:23 UTC

GitHub Revision: `eb776817a5`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 56458776725427632834749451790671712939002859133119076946547796163671543192855

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.535m	18.664ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.160s	60.780us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.230s	105.207us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	18.270s	982.953us	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.760s	508.639us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.800s	89.773us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.230s	105.207us	20	20	100.00
		kmac_csr_aliasing	9.760s	508.639us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.830s	22.803us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.560s	89.478us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	57.826m	186.160ms	50	50	100.00
V2	burst_write	kmac_burst_write	28.026m	14.009ms	48	50	96.00
V2	test_vectors	kmac_test_vectors_sha3_224	49.461m	1.703s	50	50	100.00
		kmac_test_vectors_sha3_256	43.513m	653.561ms	50	50	100.00
		kmac_test_vectors_sha3_384	32.008m	74.411ms	49	50	98.00
		kmac_test_vectors_sha3_512	25.862m	304.921ms	48	50	96.00
		kmac_test_vectors_shake_128	1.831h	2.182s	50	50	100.00
		kmac_test_vectors_shake_256	1.692h	2.212s	49	50	98.00
		kmac_test_vectors_kmac	8.220s	4.484ms	50	50	100.00
		kmac_test_vectors_kmac_xof	7.370s	269.234us	50	50	100.00
V2	sideload	kmac_sideload	9.373m	47.040ms	50	50	100.00
V2	app	kmac_app	6.603m	11.142ms	48	50	96.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.658m	31.845ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.535m	38.342ms	50	50	100.00
V2	error	kmac_error	8.268m	5.506ms	49	50	98.00
V2	key_error	kmac_key_error	15.480s	2.056ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	52.450s	8.607ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	33.040s	1.946ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.359m	28.099ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	47.540s	3.936ms	50	50	100.00
V2	stress_all	kmac_stress_all	53.137m	1.735s	46	50	92.00
V2	intr_test	kmac_intr_test	0.900s	16.605us	50	50	100.00
V2	alert_test	kmac_alert_test	0.900s	73.143us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.290s	164.980us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.290s	164.980us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.160s	60.780us	5	5	100.00
		kmac_csr_rw	1.230s	105.207us	20	20	100.00
		kmac_csr_aliasing	9.760s	508.639us	5	5	100.00
		kmac_same_csr_outstanding	2.750s	230.069us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.160s	60.780us	5	5	100.00
		kmac_csr_rw	1.230s	105.207us	20	20	100.00
		kmac_csr_aliasing	9.760s	508.639us	5	5	100.00
		kmac_same_csr_outstanding	2.750s	230.069us	20	20	100.00
V2		TOTAL			1037	1050	98.76
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.390s	44.552us	17	20	85.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.390s	44.552us	17	20	85.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.390s	44.552us	17	20	85.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.390s	44.552us	17	20	85.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.060s	236.766us	18	20	90.00
V2S	tl_intg_err	kmac_sec_cm	2.221m	77.280ms	5	5	100.00
		kmac_tl_intg_err	5.000s	775.557us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.000s	775.557us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	47.540s	3.936ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.535m	18.664ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	9.373m	47.040ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.390s	44.552us	17	20	85.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	2.221m	77.280ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	2.221m	77.280ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	2.221m	77.280ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.535m	18.664ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	47.540s	3.936ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	2.221m	77.280ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.935m	46.426ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.535m	18.664ms	50	50	100.00
V2S		TOTAL			70	75	93.33
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	57.544m	69.951ms	10	50	20.00
V3		TOTAL			10	50	20.00
		TOTAL			1232	1290	95.50

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	18	72.00
V2S	5	5	3	60.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.30	97.89	92.58	99.89	77.46	95.53	98.88	97.88

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 31 failures:
- Test kmac_stress_all_with_rand_reset has 31 failures.
  - 0.kmac_stress_all_with_rand_reset.82202973463407649431088242513847029095000315572683607252353827622966170186422
    Line 373, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5527529617 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5527529617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.kmac_stress_all_with_rand_reset.43438429165633074608090634070632238619036636215855317745555980795169912337685
    Line 951, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 137919666169 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 137919666169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 29 more failures.
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 7 failures:
- Test kmac_stress_all_with_rand_reset has 4 failures.
  - 5.kmac_stress_all_with_rand_reset.39698347678299869210881302111651749430559015926108125734769775979692710833978
    Line 366, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10034341423 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 10034341423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 17.kmac_stress_all_with_rand_reset.23791541402902832077160246760709562558798996610357054666151227034231935859812
    Line 1836, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/17.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 21828276581 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 21828276581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
- Test kmac_stress_all has 2 failures.
  - 18.kmac_stress_all.75934015288272165201567640736238429131802240438060949464111583766923924544092
    Line 1362, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 46784291653 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 46784291653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 43.kmac_stress_all.88301641312278259675247413976578045746948095751094209144500183283702351804194
    Line 980, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/43.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 172899161782 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 172899161782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_error has 1 failures.
  - 33.kmac_error.29326215106070880292921803575926569945114005716348333238050224530949183613830
    Line 759, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/33.kmac_error/latest/run.log
```
  UVM_FATAL @ 10021400776 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 10021400776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 6 failures:

Test kmac_test_vectors_shake_256 has 1 failures.

0.kmac_test_vectors_shake_256.23176927533399814750200082889331221398467601346657266795503501274354759105619
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_test_vectors_shake_256/latest/run.log

  UVM_ERROR @ 158106995 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 158106995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_test_vectors_sha3_512 has 2 failures.

14.kmac_test_vectors_sha3_512.89656803888931799291462512443386033568687575618257702738294268511493675675586
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_test_vectors_sha3_512/latest/run.log

  UVM_ERROR @  92872339 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  92872339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

36.kmac_test_vectors_sha3_512.85811750513448199795856610068882525349092941754991006610966594862883128326537
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/36.kmac_test_vectors_sha3_512/latest/run.log

  UVM_ERROR @  57338554 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  57338554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 2 failures.

14.kmac_stress_all.67741300873484126383032273119798557124034154328508188706794843640834633130710
Line 1927, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_stress_all/latest/run.log

  UVM_ERROR @ 50102062227 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 50102062227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

44.kmac_stress_all.43457119624436309709070398192141496752237269415200376186211255856834237380534
Line 908, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/44.kmac_stress_all/latest/run.log

  UVM_ERROR @ 30293553008 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 30293553008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_test_vectors_sha3_384 has 1 failures.

39.kmac_test_vectors_sha3_384.77113512123084157199112519723792489883367270289960767384231007356620683020253
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/39.kmac_test_vectors_sha3_384/latest/run.log

  UVM_ERROR @ 252942920 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 252942920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 5 failures:

Test kmac_shadow_reg_errors has 3 failures.

0.kmac_shadow_reg_errors.26510184417290379370337429000248051881155564582236392576167442091792413120271
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @   4369873 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @   4369873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

11.kmac_shadow_reg_errors.94061141109373470181341796175327860060058230695135929584548194267027617631516
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  58395099 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  58395099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test kmac_shadow_reg_errors_with_csr_rw has 2 failures.

3.kmac_shadow_reg_errors_with_csr_rw.101624174306369028879874129055467083264214850357536141480959539501684298449725
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @   8560627 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @   8560627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.kmac_shadow_reg_errors_with_csr_rw.48376381282943572865935758004634209700896435528118477759557987141865446274980
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  26783886 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  26783886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 5 failures:
- Test kmac_stress_all_with_rand_reset has 5 failures.
  - 1.kmac_stress_all_with_rand_reset.64661081841293665592286494758491802078324085451290490163055326077440473866789
    Line 263, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 191380898 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483664 [0x80000010]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 191380898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.kmac_stress_all_with_rand_reset.54913485958104859347382904772816438235770359798938364723095490520587202917307
    Line 486, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 16000632570 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483760 [0x80000070]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 16000632570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test kmac_burst_write has 2 failures.
  - 19.kmac_burst_write.48450283009162122621395977635993386664982081253812627951156131918419058252055
    Line 921, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 38.kmac_burst_write.86882009340693233915170399621904349508916185839533115627489043162223450429991
    Line 765, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/38.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 2 failures:

Test kmac_app has 2 failures.

33.kmac_app.19004062908442650110654365738912514681450795852968949535315124170197515221754
Line 281, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/33.kmac_app/latest/run.log

  UVM_FATAL @ 170437043 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (152 [0x98] vs 251 [0xfb]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 170437043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

49.kmac_app.2813528613644252157583811603444531118548580408803333385237460622868261181019
Line 519, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/49.kmac_app/latest/run.log

  UVM_FATAL @ 1882367281 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (88 [0x58] vs 175 [0xaf]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 1882367281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---