KMAC/MASKED Simulation Results

Tuesday May 21 2024 19:02:35 UTC

GitHub Revision: `be3d980075`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 85829748320245376283659198434338498577935164172956485671224275001047693479661

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.639m	23.028ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.240s	31.486us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.290s	431.133us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	21.090s	3.357ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.500s	1.921ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.820s	183.447us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.290s	431.133us	20	20	100.00
		kmac_csr_aliasing	10.500s	1.921ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.810s	148.864us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.620s	63.613us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	57.021m	96.254ms	49	50	98.00
V2	burst_write	kmac_burst_write	26.351m	15.004ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	41.709m	654.586ms	49	50	98.00
		kmac_test_vectors_sha3_256	39.782m	1.325s	48	50	96.00
		kmac_test_vectors_sha3_384	32.249m	787.136ms	50	50	100.00
		kmac_test_vectors_sha3_512	25.151m	380.284ms	49	50	98.00
		kmac_test_vectors_shake_128	1.831h	1.450s	50	50	100.00
		kmac_test_vectors_shake_256	1.547h	456.930ms	49	50	98.00
		kmac_test_vectors_kmac	9.170s	1.539ms	49	50	98.00
		kmac_test_vectors_kmac_xof	7.330s	1.277ms	50	50	100.00
V2	sideload	kmac_sideload	8.761m	44.645ms	50	50	100.00
V2	app	kmac_app	6.915m	23.486ms	48	50	96.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.557m	14.428ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.149m	64.456ms	47	50	94.00
V2	error	kmac_error	6.774m	23.672ms	50	50	100.00
V2	key_error	kmac_key_error	16.310s	12.217ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	48.360s	7.471ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	33.970s	2.981ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.097m	6.590ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	28.770s	1.577ms	50	50	100.00
V2	stress_all	kmac_stress_all	56.126m	250.757ms	49	50	98.00
V2	intr_test	kmac_intr_test	0.890s	13.144us	50	50	100.00
V2	alert_test	kmac_alert_test	0.950s	93.908us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.500s	107.503us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.500s	107.503us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.240s	31.486us	5	5	100.00
		kmac_csr_rw	1.290s	431.133us	20	20	100.00
		kmac_csr_aliasing	10.500s	1.921ms	5	5	100.00
		kmac_same_csr_outstanding	2.950s	758.578us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.240s	31.486us	5	5	100.00
		kmac_csr_rw	1.290s	431.133us	20	20	100.00
		kmac_csr_aliasing	10.500s	1.921ms	5	5	100.00
		kmac_same_csr_outstanding	2.950s	758.578us	20	20	100.00
V2		TOTAL			1037	1050	98.76
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.620s	705.843us	17	20	85.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.620s	705.843us	17	20	85.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.620s	705.843us	17	20	85.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.620s	705.843us	17	20	85.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.350s	528.383us	18	20	90.00
V2S	tl_intg_err	kmac_sec_cm	1.737m	6.672ms	5	5	100.00
		kmac_tl_intg_err	5.700s	2.585ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.700s	2.585ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	28.770s	1.577ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.639m	23.028ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	8.761m	44.645ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.620s	705.843us	17	20	85.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.737m	6.672ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.737m	6.672ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.737m	6.672ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.639m	23.028ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	28.770s	1.577ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.737m	6.672ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.896m	100.099ms	8	10	80.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.639m	23.028ms	50	50	100.00
V2S		TOTAL			68	75	90.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	52.442m	328.568ms	15	50	30.00
V3		TOTAL			15	50	30.00
		TOTAL			1235	1290	95.74

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	16	64.00
V2S	5	5	2	40.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.05	97.89	92.58	99.54	76.06	95.53	98.88	97.88

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 25 failures:
- Test kmac_stress_all_with_rand_reset has 25 failures.
  - 1.kmac_stress_all_with_rand_reset.55974733865028569084557897673615549964536308571394971590302371161395238878676
    Line 576, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 92121413178 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 92121413178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.kmac_stress_all_with_rand_reset.10705682443300605087817645194232072141914627048673777857960762016935163883986
    Line 1595, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 11527982228 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 11527982228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 23 more failures.

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 9 failures:

Test kmac_app has 2 failures.

1.kmac_app.14256271111122544532167952707072994135664423492646897816610702635829796406171
Line 413, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_app/latest/run.log

  UVM_FATAL @ 15818344535 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (148 [0x94] vs 172 [0xac]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 15818344535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

35.kmac_app.5177208765201772119052493861431921699915708824524900027752257505650646932378
Line 1041, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/35.kmac_app/latest/run.log

  UVM_FATAL @ 4635394185 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (92 [0x5c] vs 10 [0xa]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 4635394185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_mubi has 2 failures.

1.kmac_mubi.109255112688864211401561874092354788994221529893533268193058201095172283806100
Line 521, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_mubi/latest/run.log

  UVM_FATAL @ 2909652927 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (203 [0xcb] vs 35 [0x23]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 2909652927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.kmac_mubi.53526905190872857929642530199514542403014975730176986101159789230736486120602
Line 397, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_mubi/latest/run.log

  UVM_FATAL @ 1194802792 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (200 [0xc8] vs 192 [0xc0]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 1194802792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 3 failures.

2.kmac_entropy_refresh.28600171995414716323176404598158190164047395267946953823802122174743838442811
Line 521, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 4423814661 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (139 [0x8b] vs 147 [0x93]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 4423814661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.kmac_entropy_refresh.75364156503756386287371597659751030987623024193387200220398577678374970185281
Line 411, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 14970979415 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (152 [0x98] vs 149 [0x95]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 14970979415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test kmac_stress_all has 1 failures.

11.kmac_stress_all.78808056872670874373429140683976715237509359105726603353883187124599817049772
Line 345, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_stress_all/latest/run.log

  UVM_FATAL @ 6598450905 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (28 [0x1c] vs 98 [0x62]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 6598450905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all_with_rand_reset has 1 failures.

21.kmac_stress_all_with_rand_reset.18903441377011209134328262032658681214317931661120443796754840247036035878065
Line 937, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/21.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 13447146370 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (194 [0xc2] vs 32 [0x20]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 13447146370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 7 failures:
- Test kmac_stress_all_with_rand_reset has 7 failures.
  - 18.kmac_stress_all_with_rand_reset.69945677592974451044583772935333517829189569841006850258965445770759147427591
    Line 1135, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 14705118016 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483656 [0x80000008]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 14705118016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 20.kmac_stress_all_with_rand_reset.60856854985924326851548619589166818321758667560390279888768847954489109945411
    Line 1116, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/20.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 75206841416 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483736 [0x80000058]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 75206841416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 6 failures:
- Test kmac_test_vectors_kmac has 1 failures.
  - 8.kmac_test_vectors_kmac.69101649381425343839102308490942081090355221831333964921975526397519807424599
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_test_vectors_kmac/latest/run.log
```
  UVM_ERROR @  67482507 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  67482507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_sha3_224 has 1 failures.
  - 11.kmac_test_vectors_sha3_224.3193283117946965925607752885249424095677997540404645794111002471012062244689
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_test_vectors_sha3_224/latest/run.log
```
  UVM_ERROR @  61512731 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  61512731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_sha3_256 has 2 failures.
  - 14.kmac_test_vectors_sha3_256.44405042605971117703561593180900417925950910622466838964750602915036720465198
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_test_vectors_sha3_256/latest/run.log
```
  UVM_ERROR @  91066087 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  91066087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 24.kmac_test_vectors_sha3_256.72360947386949670196041685127774445190185523517670206966914903103575662039459
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/24.kmac_test_vectors_sha3_256/latest/run.log
```
  UVM_ERROR @  97293835 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  97293835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_sha3_512 has 1 failures.
  - 14.kmac_test_vectors_sha3_512.88028118696608341438660612242960249774582630998072914331904759654883284560769
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_test_vectors_sha3_512/latest/run.log
```
  UVM_ERROR @ 114093614 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 114093614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_shake_256 has 1 failures.
  - 36.kmac_test_vectors_shake_256.88227596602805632793408088292270289774376863945705044436402491230846143881006
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/36.kmac_test_vectors_shake_256/latest/run.log
```
  UVM_ERROR @ 109877096 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 109877096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 5 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 2 failures.

1.kmac_shadow_reg_errors_with_csr_rw.34875439391834132794573549322430155646224907664383420129975546354947027030472
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  33738255 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  33738255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

10.kmac_shadow_reg_errors_with_csr_rw.35136077121732589403688165402581010231551218402626192934318743971686388383979
Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  45927667 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  45927667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_shadow_reg_errors has 3 failures.

14.kmac_shadow_reg_errors.52115012552909198782862543244385713009203102525293388062882091006411510480515
Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  68352664 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  68352664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

16.kmac_shadow_reg_errors.7471808564700624265131279677808623705961458543668588095992551374886711409096
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @   1468756 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @   1468756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 2 failures:
- Test kmac_stress_all_with_rand_reset has 2 failures.
  - 2.kmac_stress_all_with_rand_reset.24313970753543130531544717146602569183938710469818787728759989530255457910429
    Line 1060, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 65129039611 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 65129039611 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 27.kmac_stress_all_with_rand_reset.32213029917235845961725382998415092025767205344505237708258429095184908311722
    Line 1086, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/27.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 48923414808 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 48923414808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test kmac_long_msg_and_output has 1 failures.
  - 32.kmac_long_msg_and_output.96436278973936225505167245803337704926494757180922817296044237079424054252597
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/32.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:018f7ddc-4e4f-4b57-86d4-ec0b0732bf7f
```