KMAC/MASKED Simulation Results

Thursday May 23 2024 19:02:32 UTC

GitHub Revision: `1579f6a912`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 107680075914347604077716278187232582575581754843183664337576824686885697334979

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.448m	18.844ms	49	50	98.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.160s	38.526us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.350s	260.982us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	10.830s	753.742us	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.300s	1.506ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.510s	43.814us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.350s	260.982us	20	20	100.00
		kmac_csr_aliasing	9.300s	1.506ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.840s	12.829us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.510s	40.847us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	long_msg_and_output	kmac_long_msg_and_output	56.943m	305.445ms	50	50	100.00
V2	burst_write	kmac_burst_write	22.955m	85.663ms	47	50	94.00
V2	test_vectors	kmac_test_vectors_sha3_224	42.090m	924.378ms	50	50	100.00
		kmac_test_vectors_sha3_256	40.015m	234.758ms	48	50	96.00
		kmac_test_vectors_sha3_384	33.822m	296.952ms	50	50	100.00
		kmac_test_vectors_sha3_512	24.875m	206.926ms	50	50	100.00
		kmac_test_vectors_shake_128	1.762h	530.391ms	50	50	100.00
		kmac_test_vectors_shake_256	1.613h	2.488s	49	50	98.00
		kmac_test_vectors_kmac	8.050s	2.685ms	50	50	100.00
		kmac_test_vectors_kmac_xof	7.150s	794.518us	50	50	100.00
V2	sideload	kmac_sideload	9.396m	24.067ms	50	50	100.00
V2	app	kmac_app	7.289m	34.612ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.589m	12.328ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.918m	87.330ms	50	50	100.00
V2	error	kmac_error	8.514m	58.521ms	47	50	94.00
V2	key_error	kmac_key_error	16.210s	7.632ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	46.620s	18.484ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	1.103m	43.236ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.102m	24.336ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	42.370s	3.651ms	50	50	100.00
V2	stress_all	kmac_stress_all	55.259m	200.127ms	46	50	92.00
V2	intr_test	kmac_intr_test	0.880s	134.071us	50	50	100.00
V2	alert_test	kmac_alert_test	0.940s	22.122us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.630s	227.790us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.630s	227.790us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.160s	38.526us	5	5	100.00
		kmac_csr_rw	1.350s	260.982us	20	20	100.00
		kmac_csr_aliasing	9.300s	1.506ms	5	5	100.00
		kmac_same_csr_outstanding	2.780s	119.626us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.160s	38.526us	5	5	100.00
		kmac_csr_rw	1.350s	260.982us	20	20	100.00
		kmac_csr_aliasing	9.300s	1.506ms	5	5	100.00
		kmac_same_csr_outstanding	2.780s	119.626us	20	20	100.00
V2		TOTAL			1037	1050	98.76
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.520s	118.895us	17	20	85.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.520s	118.895us	17	20	85.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.520s	118.895us	17	20	85.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.520s	118.895us	17	20	85.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.000s	831.854us	17	20	85.00
V2S	tl_intg_err	kmac_sec_cm	1.806m	7.652ms	5	5	100.00
		kmac_tl_intg_err	5.070s	467.232us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.070s	467.232us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	42.370s	3.651ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.448m	18.844ms	49	50	98.00
V2S	sec_cm_key_sideload	kmac_sideload	9.396m	24.067ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.520s	118.895us	17	20	85.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.806m	7.652ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.806m	7.652ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.806m	7.652ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.448m	18.844ms	49	50	98.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	42.370s	3.651ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.806m	7.652ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.649m	99.711ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.448m	18.844ms	49	50	98.00
V2S		TOTAL			69	75	92.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	54.129m	108.951ms	12	50	24.00
V3		TOTAL			12	50	24.00
		TOTAL			1232	1290	95.50

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	25	25	20	80.00
V2S	5	5	3	60.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.20	97.89	92.58	99.89	76.76	95.53	98.88	97.88

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 28 failures:
- Test kmac_stress_all_with_rand_reset has 28 failures.
  - 1.kmac_stress_all_with_rand_reset.85837618780671524520058981043890414500121292304883542830266947881252544370769
    Line 1829, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 55207458556 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 55207458556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.kmac_stress_all_with_rand_reset.36069682546096810022493982578412372291887808348747590201511256877338854176445
    Line 992, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 91614001595 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 91614001595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 26 more failures.
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 8 failures:
- Test kmac_stress_all_with_rand_reset has 8 failures.
  - 2.kmac_stress_all_with_rand_reset.78450981233862934415954983923685238661376710253229003259438978758268789464060
    Line 635, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7382137675 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483672 [0x80000018]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 7382137675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 10.kmac_stress_all_with_rand_reset.22900878872853750690819097293686654893393309059941463471880488001149127389270
    Line 1340, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 18890655343 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483680 [0x80000020]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 18890655343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 6 failures:

Test kmac_shadow_reg_errors has 3 failures.

1.kmac_shadow_reg_errors.41482860121336837097957879171319890080292953949809686377953849711655404621924
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @ 128925387 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @ 128925387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

12.kmac_shadow_reg_errors.98021022824592759232688933830232401807623863480321030103102102574301598996388
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  10634067 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  10634067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test kmac_shadow_reg_errors_with_csr_rw has 3 failures.

1.kmac_shadow_reg_errors_with_csr_rw.13048913433734078803531187484665760600172550150743981082464049702738409115191
Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  33397337 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  33397337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.kmac_shadow_reg_errors_with_csr_rw.40190763866849167921605050062070874175877008429576745857187912989090540180005
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  18108674 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  18108674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 5 failures:
- Test kmac_stress_all has 1 failures.
  - 3.kmac_stress_all.54813518899801549844367912347071345745487513708539138815321815721545622944475
    Line 508, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 24041914954 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 24041914954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_error has 2 failures.
  - 7.kmac_error.43548632214238583874816006096550096298129876427540861678265993731012023321128
    Line 293, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_error/latest/run.log
```
  UVM_FATAL @ 11006869700 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 11006869700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 38.kmac_error.28855276694224096396893884834052473536225727011376590580047725875009263672060
    Line 727, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/38.kmac_error/latest/run.log
```
  UVM_FATAL @ 10130613161 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 10130613161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_stress_all_with_rand_reset has 2 failures.
  - 36.kmac_stress_all_with_rand_reset.75727925949273182334507855346551284491662011485711101424347208682905139388873
    Line 785, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/36.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 54273825437 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 54273825437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 40.kmac_stress_all_with_rand_reset.13403634693655633185618746770743577542229735854165137557779987295004577611862
    Line 1922, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/40.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 175601566708 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 175601566708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 5 failures:

Test kmac_test_vectors_sha3_256 has 2 failures.

19.kmac_test_vectors_sha3_256.107351767842117293500100829218579260969267860903574495171058365076995405904403
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_test_vectors_sha3_256/latest/run.log

  UVM_ERROR @  26064166 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  26064166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

24.kmac_test_vectors_sha3_256.26071697868663021478403784534786357020434212654300946558502274963531061041020
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/24.kmac_test_vectors_sha3_256/latest/run.log

  UVM_ERROR @  52059289 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  52059289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 1 failures.

19.kmac_stress_all.102648822640300268012013952644771240347603499760239817252470109884006852475393
Line 1190, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_stress_all/latest/run.log

  UVM_ERROR @ 23903912725 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 23903912725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_smoke has 1 failures.

32.kmac_smoke.107772835585807698114149946860881975262286805539757939122901718101993922602307
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/32.kmac_smoke/latest/run.log

  UVM_ERROR @  80074183 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  80074183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_test_vectors_shake_256 has 1 failures.

49.kmac_test_vectors_shake_256.31097717165870489399997120456287102160381512608596037132876475563307109170399
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/49.kmac_test_vectors_shake_256/latest/run.log

  UVM_ERROR @  37925983 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  37925983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
- Test kmac_error has 1 failures.
  - 2.kmac_error.60784864484939997597983732579566606318215590233375663778474232193150798442760
    Line 1199, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_error/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_burst_write has 3 failures.
  - 14.kmac_burst_write.97007354283929616156861353093989566692270263028020237984105201400446385009761
    Line 698, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 31.kmac_burst_write.73930900092303582038945733945752693833001413176611284573726957383280229388300
    Line 1196, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/31.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 2 failures:

Test kmac_stress_all has 2 failures.

8.kmac_stress_all.88056523186497414518338643046190384027116375325287222528319506411210203068613
Line 819, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_stress_all/latest/run.log

  UVM_FATAL @ 84935386653 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (76 [0x4c] vs 22 [0x16]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 84935386653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

48.kmac_stress_all.79036644573738973487985041671518231562566332766297593116856445771153688432461
Line 1725, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/48.kmac_stress_all/latest/run.log

  UVM_FATAL @ 19010964661 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (87 [0x57] vs 173 [0xad]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 19010964661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---