KMAC/MASKED Simulation Results

Sunday May 26 2024 19:04:10 UTC

GitHub Revision: `2cf28c40e5`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 76231542290686940289653487239061276463019235878731279188279352215076078972419

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.510m	4.849ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.110s	44.383us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.220s	99.058us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	20.870s	1.497ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.560s	419.259us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.700s	71.281us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.220s	99.058us	20	20	100.00
		kmac_csr_aliasing	7.560s	419.259us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.760s	15.361us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.570s	40.450us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	58.468m	512.089ms	50	50	100.00
V2	burst_write	kmac_burst_write	29.760m	35.158ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	42.240m	424.547ms	49	50	98.00
		kmac_test_vectors_sha3_256	38.836m	329.068ms	50	50	100.00
		kmac_test_vectors_sha3_384	33.020m	293.213ms	49	50	98.00
		kmac_test_vectors_sha3_512	23.557m	204.706ms	50	50	100.00
		kmac_test_vectors_shake_128	1.839h	2.549s	49	50	98.00
		kmac_test_vectors_shake_256	1.590h	1.282s	49	50	98.00
		kmac_test_vectors_kmac	6.990s	1.410ms	50	50	100.00
		kmac_test_vectors_kmac_xof	6.820s	1.302ms	50	50	100.00
V2	sideload	kmac_sideload	9.226m	52.106ms	50	50	100.00
V2	app	kmac_app	7.140m	102.108ms	48	50	96.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.113m	28.831ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	8.076m	28.587ms	49	50	98.00
V2	error	kmac_error	9.844m	22.390ms	50	50	100.00
V2	key_error	kmac_key_error	14.000s	3.091ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	49.110s	1.978ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	1.019m	6.989ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.308m	7.257ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	46.770s	700.906us	50	50	100.00
V2	stress_all	kmac_stress_all	48.119m	101.787ms	46	50	92.00
V2	intr_test	kmac_intr_test	0.900s	17.489us	50	50	100.00
V2	alert_test	kmac_alert_test	0.960s	32.761us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.400s	466.171us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.400s	466.171us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.110s	44.383us	5	5	100.00
		kmac_csr_rw	1.220s	99.058us	20	20	100.00
		kmac_csr_aliasing	7.560s	419.259us	5	5	100.00
		kmac_same_csr_outstanding	2.610s	104.851us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.110s	44.383us	5	5	100.00
		kmac_csr_rw	1.220s	99.058us	20	20	100.00
		kmac_csr_aliasing	7.560s	419.259us	5	5	100.00
		kmac_same_csr_outstanding	2.610s	104.851us	20	20	100.00
V2		TOTAL			1039	1050	98.95
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.250s	34.422us	15	20	75.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.250s	34.422us	15	20	75.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.250s	34.422us	15	20	75.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.250s	34.422us	15	20	75.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.140s	139.676us	17	20	85.00
V2S	tl_intg_err	kmac_sec_cm	1.862m	31.142ms	5	5	100.00
		kmac_tl_intg_err	5.230s	1.535ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.230s	1.535ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	46.770s	700.906us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.510m	4.849ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	9.226m	52.106ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.250s	34.422us	15	20	75.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.862m	31.142ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.862m	31.142ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.862m	31.142ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.510m	4.849ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	46.770s	700.906us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.862m	31.142ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.966m	52.593ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.510m	4.849ms	50	50	100.00
V2S		TOTAL			67	75	89.33
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	54.380m	81.664ms	13	50	26.00
V3		TOTAL			13	50	26.00
		TOTAL			1234	1290	95.66

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	18	72.00
V2S	5	5	3	60.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.03	97.91	92.52	99.89	75.35	95.59	99.05	97.88

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 28 failures:
- Test kmac_stress_all_with_rand_reset has 28 failures.
  - 0.kmac_stress_all_with_rand_reset.56971178980245906475822158356508468756479325951425935162730566607068466637429
    Line 1120, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 70284530638 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 70284530638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.58070171728186202202696951732929325015442677096189626240820588331281382999910
    Line 551, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 17109932955 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 17109932955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 26 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 8 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 3 failures.

0.kmac_shadow_reg_errors_with_csr_rw.52398121003649048820468072001381957236231149691371438073514957444733914279414
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @   7538669 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @   7538669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.kmac_shadow_reg_errors_with_csr_rw.92589712676202861744833711158426883673903637689268378307493829838131764425768
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  16123882 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  16123882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test kmac_shadow_reg_errors has 5 failures.

3.kmac_shadow_reg_errors.115780557294074545426620623861249210623550048583040459951445095037178888455283
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  46458901 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  46458901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.kmac_shadow_reg_errors.106373074736787602462379899178609805576273407107933476299309418687041465648030
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  14124029 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  14124029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 8 failures:
- Test kmac_stress_all_with_rand_reset has 8 failures.
  - 18.kmac_stress_all_with_rand_reset.20475912637718334319055978854183398234530529625333716452361631514651431874009
    Line 1969, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 17135969914 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483672 [0x80000018]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 17135969914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 19.kmac_stress_all_with_rand_reset.3424209401882000590804176087795368102689063377308452567112277080276126301909
    Line 1009, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 55715481590 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483712 [0x80000040]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 55715481590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 6 failures:

Test kmac_test_vectors_sha3_384 has 1 failures.

2.kmac_test_vectors_sha3_384.37128513397518226548043305474274241192445388015243454472965378638945256271737
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_384/latest/run.log

  UVM_ERROR @  52118965 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  52118965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 2 failures.

2.kmac_stress_all.48226441952200519952735407248714419684108157245678062099926805402511548988647
Line 1356, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all/latest/run.log

  UVM_ERROR @ 60318233720 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 60318233720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

31.kmac_stress_all.45987341829703048363585290311564917063368387451149956877734739295209820796978
Line 733, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/31.kmac_stress_all/latest/run.log

  UVM_ERROR @ 19877777441 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 19877777441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_test_vectors_sha3_224 has 1 failures.

4.kmac_test_vectors_sha3_224.71543642500497965645250075016864579203700478248603197105153515995387184890552
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_224/latest/run.log

  UVM_ERROR @ 137273671 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 137273671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_test_vectors_shake_128 has 1 failures.

27.kmac_test_vectors_shake_128.107375753158777307743689855480628699217163515512042618150413779532840330391812
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/27.kmac_test_vectors_shake_128/latest/run.log

  UVM_ERROR @  39675899 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  39675899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_test_vectors_shake_256 has 1 failures.

30.kmac_test_vectors_shake_256.49168700780944979727475588186934260202241906407786546721360810738047391478661
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/30.kmac_test_vectors_shake_256/latest/run.log

  UVM_ERROR @  41969450 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  41969450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 3 failures:
- Test kmac_stress_all has 2 failures.
  - 10.kmac_stress_all.17212128974493555476930512472838803076391023698511162854000222279663573002498
    Line 760, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 18363627107 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 18363627107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 24.kmac_stress_all.81005771712803063003280876958363025439617509467618916039332882776158494140204
    Line 1438, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/24.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 190528293583 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 190528293583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 40.kmac_stress_all_with_rand_reset.71652475491809830318980888278751144059133948129648811702875572031390861722159
    Line 4214, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/40.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 74061977380 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 74061977380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 2 failures:
- Test kmac_entropy_refresh has 1 failures.
  - 26.kmac_entropy_refresh.62949439172001890195570796036368530938215087323805597751470745513594057917129
    Line 283, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/26.kmac_entropy_refresh/latest/run.log
```
  UVM_FATAL @ 3809031331 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (129 [0x81] vs 137 [0x89]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 3809031331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_app has 1 failures.
  - 34.kmac_app.44634523559435606658777168247673707585599608131637836658419277863463732656807
    Line 823, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/34.kmac_app/latest/run.log
```
  UVM_FATAL @ 26456130508 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (58 [0x3a] vs 64 [0x40]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 26456130508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_app has 1 failures.
  - 1.kmac_app.69712799595279019546865575730581550626244659950510252995447315114235683069583
    Line 1024, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_app/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```