KMAC/MASKED Simulation Results

Tuesday May 28 2024 19:30:06 UTC

GitHub Revision: `0e5093d709`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 51604449886868634540233838791789448907774502353938218657919214072353062987195

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.603m	34.352ms	49	50	98.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.160s	119.028us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.280s	50.210us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	21.770s	1.511ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	8.720s	2.602ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.650s	722.802us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.280s	50.210us	20	20	100.00
		kmac_csr_aliasing	8.720s	2.602ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.770s	21.769us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.470s	36.573us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	long_msg_and_output	kmac_long_msg_and_output	57.052m	353.541ms	49	50	98.00
V2	burst_write	kmac_burst_write	24.513m	25.245ms	47	50	94.00
V2	test_vectors	kmac_test_vectors_sha3_224	49.513m	1.911s	50	50	100.00
		kmac_test_vectors_sha3_256	41.950m	894.362ms	49	50	98.00
		kmac_test_vectors_sha3_384	33.655m	698.769ms	49	50	98.00
		kmac_test_vectors_sha3_512	24.043m	675.627ms	50	50	100.00
		kmac_test_vectors_shake_128	1.864h	925.734ms	49	50	98.00
		kmac_test_vectors_shake_256	1.653h	919.130ms	49	50	98.00
		kmac_test_vectors_kmac	7.500s	935.816us	49	50	98.00
		kmac_test_vectors_kmac_xof	7.670s	827.027us	49	50	98.00
V2	sideload	kmac_sideload	9.676m	124.537ms	50	50	100.00
V2	app	kmac_app	7.096m	77.523ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.599m	21.779ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.052m	42.392ms	47	50	94.00
V2	error	kmac_error	8.460m	58.166ms	48	50	96.00
V2	key_error	kmac_key_error	19.340s	28.985ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	49.210s	7.506ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	45.900s	8.556ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.199m	24.475ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	56.820s	3.051ms	50	50	100.00
V2	stress_all	kmac_stress_all	50.078m	171.094ms	44	50	88.00
V2	intr_test	kmac_intr_test	0.890s	38.530us	50	50	100.00
V2	alert_test	kmac_alert_test	0.920s	65.888us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.370s	403.910us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.370s	403.910us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.160s	119.028us	5	5	100.00
		kmac_csr_rw	1.280s	50.210us	20	20	100.00
		kmac_csr_aliasing	8.720s	2.602ms	5	5	100.00
		kmac_same_csr_outstanding	2.790s	132.116us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.160s	119.028us	5	5	100.00
		kmac_csr_rw	1.280s	50.210us	20	20	100.00
		kmac_csr_aliasing	8.720s	2.602ms	5	5	100.00
		kmac_same_csr_outstanding	2.790s	132.116us	20	20	100.00
V2		TOTAL			1028	1050	97.90
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.330s	66.981us	17	20	85.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.330s	66.981us	17	20	85.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.330s	66.981us	17	20	85.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.330s	66.981us	17	20	85.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.090s	135.725us	16	20	80.00
V2S	tl_intg_err	kmac_sec_cm	1.743m	6.931ms	5	5	100.00
		kmac_tl_intg_err	5.170s	272.168us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.170s	272.168us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	56.820s	3.051ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.603m	34.352ms	49	50	98.00
V2S	sec_cm_key_sideload	kmac_sideload	9.676m	124.537ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.330s	66.981us	17	20	85.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.743m	6.931ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.743m	6.931ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.743m	6.931ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.603m	34.352ms	49	50	98.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	56.820s	3.051ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.743m	6.931ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.522m	182.791ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.603m	34.352ms	49	50	98.00
V2S		TOTAL			68	75	90.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	40.820m	32.326ms	13	50	26.00
V3		TOTAL			13	50	26.00
		TOTAL			1223	1290	94.81

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	25	25	13	52.00
V2S	5	5	3	60.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.34	97.91	92.62	99.89	77.46	95.59	99.05	97.88

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 27 failures:
- Test kmac_stress_all_with_rand_reset has 27 failures.
  - 0.kmac_stress_all_with_rand_reset.3046602473083267744444822723800798448601117663822923837369761874295335305052
    Line 299, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2753849371 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2753849371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.23170119520313178446824454073359280373153911892798249082441881531435917615444
    Line 1606, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 372216656562 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 372216656562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 25 more failures.
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 9 failures:
- Test kmac_stress_all_with_rand_reset has 9 failures.
  - 2.kmac_stress_all_with_rand_reset.4016922640555957929752895189581142128710637140064666118756184904138859132778
    Line 1813, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 18032455401 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483736 [0x80000058]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 18032455401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.kmac_stress_all_with_rand_reset.32845489541361499023234393996336350779633666265048116997289046761836763236032
    Line 2346, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 18094888292 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483712 [0x80000040]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 18094888292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 7 failures:
- Test kmac_test_vectors_sha3_384 has 1 failures.
  - 0.kmac_test_vectors_sha3_384.30513720158117938029551491385688736171635412528869759079917550255619816335462
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_384/latest/run.log
```
  UVM_ERROR @  53226207 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  53226207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_shake_256 has 1 failures.
  - 0.kmac_test_vectors_shake_256.83180429320107368634684002650322420057944642960689709675299952042247293185112
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_test_vectors_shake_256/latest/run.log
```
  UVM_ERROR @  71828049 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  71828049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_kmac_xof has 1 failures.
  - 23.kmac_test_vectors_kmac_xof.24517508170292975894770410272986218197459968866461226979295059766754581931141
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_test_vectors_kmac_xof/latest/run.log
```
  UVM_ERROR @  44209174 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  44209174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_sha3_256 has 1 failures.
  - 29.kmac_test_vectors_sha3_256.9777011317962789349537316370307813329452048380267672435530007749672193938012
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/29.kmac_test_vectors_sha3_256/latest/run.log
```
  UVM_ERROR @  31049788 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  31049788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_shake_128 has 1 failures.
  - 30.kmac_test_vectors_shake_128.17597219128634048873106915158723959972650536951268085059025927925214037075498
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/30.kmac_test_vectors_shake_128/latest/run.log
```
  UVM_ERROR @ 112774537 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 112774537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 2 more tests.

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 7 failures:

Test kmac_entropy_refresh has 3 failures.

1.kmac_entropy_refresh.38193983846715328786907833402004130429023351790230976613005912758330158822907
Line 417, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 3485698948 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (48 [0x30] vs 123 [0x7b]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 3485698948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

35.kmac_entropy_refresh.91952619392336613529022594086071098786143950357161273455578113343698549981813
Line 455, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/35.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 6246894748 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (154 [0x9a] vs 229 [0xe5]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 6246894748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test kmac_stress_all has 3 failures.

4.kmac_stress_all.37873187364346169943911562546379923226100442371460384573775843387572437934889
Line 701, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_stress_all/latest/run.log

  UVM_FATAL @ 35989108661 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (216 [0xd8] vs 217 [0xd9]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 35989108661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.kmac_stress_all.50419288456188206074775579980626109037475863936021075335332266115834360446703
Line 567, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_stress_all/latest/run.log

  UVM_FATAL @ 9555924336 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (163 [0xa3] vs 21 [0x15]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 9555924336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test kmac_app has 1 failures.

29.kmac_app.28767369524815284171462916113214623356680553873421572705596695581009618522084
Line 521, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/29.kmac_app/latest/run.log

  UVM_FATAL @ 4254995470 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (245 [0xf5] vs 145 [0x91]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 4254995470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 7 failures:

Test kmac_shadow_reg_errors has 3 failures.

3.kmac_shadow_reg_errors.74740011549723261136595616279615144064032722405226363130953582050939419315171
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @   9543574 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @   9543574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.kmac_shadow_reg_errors.40330934148615883836966063889904486729540422161327726322527972884292778107240
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @   3295894 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @   3295894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test kmac_shadow_reg_errors_with_csr_rw has 4 failures.

3.kmac_shadow_reg_errors_with_csr_rw.4216151979920855528785202821180532287911918469175953121279762099794922798282
Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  29276910 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  29276910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.kmac_shadow_reg_errors_with_csr_rw.31678896651931501840191060304169877285122611835537404836450775320806270981622
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  51102647 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  51102647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 5 failures:
- Test kmac_stress_all has 3 failures.
  - 0.kmac_stress_all.37871158049072461779246947551497180238081652590445421873977872934815122280861
    Line 670, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 30092999477 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 30092999477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.kmac_stress_all.66207092484900077732866858591120318447190142807876542005958520010799092798657
    Line 967, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 153021820362 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 153021820362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test kmac_error has 1 failures.
  - 2.kmac_error.98948631180996704683685267117416708123629742395890465706849139139916117227749
    Line 395, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_error/latest/run.log
```
  UVM_FATAL @ 10139523942 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 10139523942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 17.kmac_stress_all_with_rand_reset.113703008054528610953560463399922133347731252071378123809999564351748333784136
    Line 1974, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/17.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 65958233645 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 65958233645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
- Test kmac_burst_write has 3 failures.
  - 19.kmac_burst_write.54930114340829866831168081332038063757845846184906933977237621393284822605191
    Line 986, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 37.kmac_burst_write.40267480006555679723013741321811474508808816956332987988423374362515888044494
    Line 693, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/37.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test kmac_error has 1 failures.
  - 22.kmac_error.66883765603752140764889825014436450664598948633777322663721303553484420553975
    Line 1142, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/22.kmac_error/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test kmac_long_msg_and_output has 1 failures.
  - 43.kmac_long_msg_and_output.45662972947966230006552303364785582202481724478095758772175885863141502297700
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/43.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:f095ff36-d087-4d42-8ca9-b534ea420ef6
```