KMAC/MASKED Simulation Results

Thursday May 30 2024 19:02:59 UTC

GitHub Revision: `8cb25a6867`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 26638040090898561482658723926798947801831709189350919955228328310045202344042

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	2.016m	24.883ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.190s	109.039us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.270s	171.387us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	22.770s	6.576ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.510s	513.558us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.690s	217.284us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.270s	171.387us	20	20	100.00
		kmac_csr_aliasing	9.510s	513.558us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.830s	44.103us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.300s	43.709us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	55.360m	744.534ms	50	50	100.00
V2	burst_write	kmac_burst_write	24.230m	57.923ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	42.890m	465.694ms	49	50	98.00
		kmac_test_vectors_sha3_256	41.433m	187.316ms	50	50	100.00
		kmac_test_vectors_sha3_384	32.141m	286.458ms	50	50	100.00
		kmac_test_vectors_sha3_512	23.710m	50.812ms	48	50	96.00
		kmac_test_vectors_shake_128	1.782h	1.070s	48	50	96.00
		kmac_test_vectors_shake_256	1.559h	363.791ms	50	50	100.00
		kmac_test_vectors_kmac	8.130s	4.004ms	49	50	98.00
		kmac_test_vectors_kmac_xof	7.430s	834.511us	50	50	100.00
V2	sideload	kmac_sideload	9.587m	64.143ms	49	50	98.00
V2	app	kmac_app	6.822m	19.436ms	48	50	96.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.039m	14.025ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.104m	8.589ms	50	50	100.00
V2	error	kmac_error	9.418m	56.567ms	49	50	98.00
V2	key_error	kmac_key_error	17.740s	18.073ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	58.460s	31.364ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	51.810s	5.149ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.277m	6.823ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	53.120s	963.747us	50	50	100.00
V2	stress_all	kmac_stress_all	50.473m	390.851ms	47	50	94.00
V2	intr_test	kmac_intr_test	0.870s	16.764us	50	50	100.00
V2	alert_test	kmac_alert_test	0.940s	37.159us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.790s	576.538us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.790s	576.538us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.190s	109.039us	5	5	100.00
		kmac_csr_rw	1.270s	171.387us	20	20	100.00
		kmac_csr_aliasing	9.510s	513.558us	5	5	100.00
		kmac_same_csr_outstanding	3.100s	968.524us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.190s	109.039us	5	5	100.00
		kmac_csr_rw	1.270s	171.387us	20	20	100.00
		kmac_csr_aliasing	9.510s	513.558us	5	5	100.00
		kmac_same_csr_outstanding	3.100s	968.524us	20	20	100.00
V2		TOTAL			1037	1050	98.76
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.480s	65.605us	19	20	95.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.480s	65.605us	19	20	95.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.480s	65.605us	19	20	95.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.480s	65.605us	19	20	95.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.230s	534.922us	19	20	95.00
V2S	tl_intg_err	kmac_sec_cm	1.400m	27.082ms	5	5	100.00
		kmac_tl_intg_err	5.270s	260.304us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.270s	260.304us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	53.120s	963.747us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	2.016m	24.883ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	9.587m	64.143ms	49	50	98.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.480s	65.605us	19	20	95.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.400m	27.082ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.400m	27.082ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.400m	27.082ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	2.016m	24.883ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	53.120s	963.747us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.400m	27.082ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	7.109m	13.938ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	2.016m	24.883ms	50	50	100.00
V2S		TOTAL			73	75	97.33
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	58.786m	71.948ms	19	50	38.00
V3		TOTAL			19	50	38.00
		TOTAL			1244	1290	96.43

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	17	68.00
V2S	5	5	3	60.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.40	97.89	92.58	99.89	78.17	95.53	98.89	97.88

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:
- Test kmac_stress_all_with_rand_reset has 23 failures.
  - 0.kmac_stress_all_with_rand_reset.7557413310102538689587163733907750263817155229283238697922535987964146486300
    Line 619, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 63656909936 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 63656909936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.kmac_stress_all_with_rand_reset.33466083738852852077912684400823878210840650887258384247104282278873639418208
    Line 292, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 13192741477 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 13192741477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 21 more failures.
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 8 failures:
- Test kmac_stress_all_with_rand_reset has 8 failures.
  - 1.kmac_stress_all_with_rand_reset.101159246481132416182468292451165603026986267860374683302758009607138221099623
    Line 1679, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 66391144479 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483680 [0x80000020]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 66391144479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.kmac_stress_all_with_rand_reset.112040655749960606909586538164775948594187654162097440708388438954866668938246
    Line 428, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7681886108 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483656 [0x80000008]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 7681886108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 6 failures:

Test kmac_test_vectors_kmac has 1 failures.

0.kmac_test_vectors_kmac.30005635424240902454450411771487825669982365302838138132430753139771007094959
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_test_vectors_kmac/latest/run.log

  UVM_ERROR @  90954149 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  90954149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_test_vectors_sha3_512 has 2 failures.

17.kmac_test_vectors_sha3_512.30718705679291800563483254391389309282237200461594776720669083282460032005330
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/17.kmac_test_vectors_sha3_512/latest/run.log

  UVM_ERROR @  24503910 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  24503910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

24.kmac_test_vectors_sha3_512.14953095237068735650738308437837814808172954982347015312080728107304065706676
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/24.kmac_test_vectors_sha3_512/latest/run.log

  UVM_ERROR @  51294881 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  51294881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_test_vectors_shake_128 has 1 failures.

23.kmac_test_vectors_shake_128.35006596782549985112979180221607212882775186645107927013376066302652726390265
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_test_vectors_shake_128/latest/run.log

  UVM_ERROR @  35134675 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  35134675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_sideload has 1 failures.

35.kmac_sideload.74424733569897426475863009084445136170816127530273113925260984984954500882783
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/35.kmac_sideload/latest/run.log

  UVM_ERROR @  97828935 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  97828935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_test_vectors_sha3_224 has 1 failures.

46.kmac_test_vectors_sha3_224.55094202418330759661584483092842553458891535848404104388417792735611495567860
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/46.kmac_test_vectors_sha3_224/latest/run.log

  UVM_ERROR @  44562618 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  44562618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 4 failures:

Test kmac_app has 2 failures.

5.kmac_app.82377852346706289703056323998625939828623492648443522244842467165750398396676
Line 373, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_app/latest/run.log

  UVM_FATAL @ 7297264498 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (134 [0x86] vs 34 [0x22]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 7297264498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

42.kmac_app.16451134483467119937711398156802406766797074670718569380319526378409108843377
Line 543, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/42.kmac_app/latest/run.log

  UVM_FATAL @ 3640081123 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (46 [0x2e] vs 43 [0x2b]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 3640081123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 2 failures.

28.kmac_stress_all.16489304231090398611096524662305290392703827322430029483088973479190558518206
Line 383, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/28.kmac_stress_all/latest/run.log

  UVM_FATAL @ 2324613208 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (184 [0xb8] vs 170 [0xaa]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 2324613208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

44.kmac_stress_all.78485872245522875833909212542421334764090490407984713438822103727748582928328
Line 581, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/44.kmac_stress_all/latest/run.log

  UVM_FATAL @ 30126887043 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (115 [0x73] vs 112 [0x70]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 30126887043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 2 failures:
- Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.
  - 1.kmac_shadow_reg_errors_with_csr_rw.108706657850937831217573337862120265362244821161142221099608535562797196131797
    Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @  34819875 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  34819875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_shadow_reg_errors has 1 failures.
  - 6.kmac_shadow_reg_errors.34306187034288573319443897217838465026345846713508496234097287197277280141363
    Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_shadow_reg_errors/latest/run.log
```
  UVM_ERROR @  42987304 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  42987304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 2 failures:
- Test kmac_stress_all has 1 failures.
  - 24.kmac_stress_all.67914458843138975862430627924030050990238941471244515116596141062743265631734
    Line 478, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/24.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 13482092426 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 13482092426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_error has 1 failures.
  - 37.kmac_error.98099185727174649195044847325148358998759111619703197908629646368147602260490
    Line 765, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/37.kmac_error/latest/run.log
```
  UVM_FATAL @ 10100890504 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 10100890504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_test_vectors_shake_128 has 1 failures.
  - 15.kmac_test_vectors_shake_128.85040345037177706881301104307704713847352198904525550702725406331169705151964
    Line 5942, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_test_vectors_shake_128/latest/run.log
```
  UVM_FATAL @ 5000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 5000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 5000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```