KMAC/MASKED Simulation Results

Sunday June 02 2024 19:02:53 UTC

GitHub Revision: `01a208901a`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 50418669159766293903157726892781832882154091083197082086235277423705989875584

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.432m	10.408ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.060s	292.565us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.300s	113.309us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	22.200s	1.453ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.160s	550.020us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.720s	133.680us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.300s	113.309us	20	20	100.00
		kmac_csr_aliasing	10.160s	550.020us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.780s	22.410us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.370s	39.202us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	58.538m	133.823ms	49	50	98.00
V2	burst_write	kmac_burst_write	31.490m	32.964ms	46	50	92.00
V2	test_vectors	kmac_test_vectors_sha3_224	41.782m	103.185ms	48	50	96.00
		kmac_test_vectors_sha3_256	44.606m	1.565s	50	50	100.00
		kmac_test_vectors_sha3_384	33.045m	572.542ms	50	50	100.00
		kmac_test_vectors_sha3_512	23.981m	212.547ms	50	50	100.00
		kmac_test_vectors_shake_128	1.730h	382.484ms	49	50	98.00
		kmac_test_vectors_shake_256	1.492h	912.005ms	50	50	100.00
		kmac_test_vectors_kmac	7.220s	4.306ms	49	50	98.00
		kmac_test_vectors_kmac_xof	7.300s	2.837ms	50	50	100.00
V2	sideload	kmac_sideload	9.056m	42.590ms	50	50	100.00
V2	app	kmac_app	6.990m	25.507ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.423m	180.544ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.853m	17.166ms	48	50	96.00
V2	error	kmac_error	8.676m	6.303ms	50	50	100.00
V2	key_error	kmac_key_error	15.910s	4.322ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	48.950s	1.469ms	19	20	95.00
V2	entropy_mode_error	kmac_entropy_mode_error	45.560s	1.470ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.348m	7.413ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	31.310s	2.995ms	50	50	100.00
V2	stress_all	kmac_stress_all	46.280m	214.765ms	48	50	96.00
V2	intr_test	kmac_intr_test	0.950s	42.782us	50	50	100.00
V2	alert_test	kmac_alert_test	0.950s	20.120us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.310s	132.555us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.310s	132.555us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.060s	292.565us	5	5	100.00
		kmac_csr_rw	1.300s	113.309us	20	20	100.00
		kmac_csr_aliasing	10.160s	550.020us	5	5	100.00
		kmac_same_csr_outstanding	2.600s	354.215us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.060s	292.565us	5	5	100.00
		kmac_csr_rw	1.300s	113.309us	20	20	100.00
		kmac_csr_aliasing	10.160s	550.020us	5	5	100.00
		kmac_same_csr_outstanding	2.600s	354.215us	20	20	100.00
V2		TOTAL			1035	1050	98.57
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.450s	103.060us	17	20	85.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.450s	103.060us	17	20	85.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.450s	103.060us	17	20	85.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.450s	103.060us	17	20	85.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.860s	128.866us	19	20	95.00
V2S	tl_intg_err	kmac_sec_cm	1.402m	5.565ms	5	5	100.00
		kmac_tl_intg_err	5.170s	274.409us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.170s	274.409us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	31.310s	2.995ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.432m	10.408ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	9.056m	42.590ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.450s	103.060us	17	20	85.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.402m	5.565ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.402m	5.565ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.402m	5.565ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.432m	10.408ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	31.310s	2.995ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.402m	5.565ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.784m	16.415ms	8	10	80.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.432m	10.408ms	50	50	100.00
V2S		TOTAL			69	75	92.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	41.338m	117.606ms	12	50	24.00
V3		TOTAL			12	50	24.00
		TOTAL			1231	1290	95.43

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	16	64.00
V2S	5	5	2	40.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.14	97.91	92.65	99.89	76.06	95.59	99.05	97.88

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 27 failures:
- Test kmac_stress_all_with_rand_reset has 27 failures.
  - 0.kmac_stress_all_with_rand_reset.46445596784984475610025402901559621443306009447511407674084722080379562822360
    Line 551, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 258146528608 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 258146528608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.100974137268851821085361765070323296240664828664779158911761473682338588631575
    Line 1455, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 36343624965 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 36343624965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 25 more failures.
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 11 failures:
- Test kmac_stress_all_with_rand_reset has 11 failures.
  - 2.kmac_stress_all_with_rand_reset.72376085748954656563721773966684565375236236623413083675219785932060529219181
    Line 371, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1506344447 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483680 [0x80000020]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 1506344447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.kmac_stress_all_with_rand_reset.84846522231115585038711575844690855140401537906123693275888273038251045808205
    Line 261, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  13059106 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483704 [0x80000038]) reg name: kmac_reg_block.err_code
  UVM_INFO @  13059106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 6 failures:

Test kmac_test_vectors_shake_128 has 1 failures.

8.kmac_test_vectors_shake_128.69280039791398910972387649535364960200575596626873221832363089749388742096489
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_test_vectors_shake_128/latest/run.log

  UVM_ERROR @  33312429 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  33312429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 1 failures.

22.kmac_entropy_refresh.19482305949716458645980285666064138105940445635326591650560516672966027528997
Line 680, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/22.kmac_entropy_refresh/latest/run.log

  UVM_ERROR @ 13804137599 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 13804137599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 1 failures.

32.kmac_stress_all.30750582594589738323110790777817261782819203721273711386695926614262364198758
Line 1250, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/32.kmac_stress_all/latest/run.log

  UVM_ERROR @ 68334782962 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 68334782962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_test_vectors_sha3_224 has 2 failures.

35.kmac_test_vectors_sha3_224.34081443285593186354324936952879561479584906174009602896938020238685317486013
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/35.kmac_test_vectors_sha3_224/latest/run.log

  UVM_ERROR @  24673274 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  24673274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

42.kmac_test_vectors_sha3_224.44275345417529635963815471183442760751885765212692126718506353351668172271760
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/42.kmac_test_vectors_sha3_224/latest/run.log

  UVM_ERROR @  98555633 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  98555633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_test_vectors_kmac has 1 failures.

41.kmac_test_vectors_kmac.15764510238840236109462494294354935464074206260078475664625709897894537153018
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/41.kmac_test_vectors_kmac/latest/run.log

  UVM_ERROR @  69421054 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  69421054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 4 failures:

Test kmac_mubi has 2 failures.

1.kmac_mubi.14667989358247609017541328695633222527383145880687013673792722497209648790710
Line 745, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_mubi/latest/run.log

  UVM_FATAL @ 47765286836 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (89 [0x59] vs 61 [0x3d]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 47765286836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.kmac_mubi.7544211241988630894826202949813918640978266547301021121380789224293315392164
Line 625, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_mubi/latest/run.log

  UVM_FATAL @ 2560434146 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (122 [0x7a] vs 247 [0xf7]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 2560434146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 1 failures.

30.kmac_entropy_refresh.51468257451657277120921048060274439966597371588727476811269591667407883644812
Line 745, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/30.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 39672204383 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (168 [0xa8] vs 158 [0x9e]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 39672204383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 1 failures.

33.kmac_app.68259437358695074307552619490636380530666988013649795350279744202227164950691
Line 693, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/33.kmac_app/latest/run.log

  UVM_FATAL @ 11854809282 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (29 [0x1d] vs 52 [0x34]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 11854809282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
- Test kmac_burst_write has 4 failures.
  - 4.kmac_burst_write.88596431329915389990495135256694663119377387629050064662475533802711665160525
    Line 1040, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 24.kmac_burst_write.72259334126350819449579965039770820076769864301208543097513263978544545272100
    Line 1046, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/24.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 4 failures:

Test kmac_shadow_reg_errors has 3 failures.

6.kmac_shadow_reg_errors.110387584342538557210756066692662147137780337423000365102450530393508749552296
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  17382876 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  17382876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

14.kmac_shadow_reg_errors.74530482246343023266400406831159487339620776558444651826551963740363572433723
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  74968425 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  74968425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

13.kmac_shadow_reg_errors_with_csr_rw.92272607517058283343263181958254581163440361260814247354221975263561143778609
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  13663346 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  13663346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (kmac_edn_timeout_error_vseq.sv:68) [kmac_edn_timeout_error_vseq] Check failed cfg.m_kmac_app_agent_cfg[AppKeymgr].vif.kmac_data_rsp.error == * (* [*] vs * [*]) has 1 failures:
- Test kmac_edn_timeout_error has 1 failures.
  - 10.kmac_edn_timeout_error.105480190072034030461108982449841228063356118737215511043229766840775413596573
    Line 260, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_edn_timeout_error/latest/run.log
```
  UVM_ERROR @ 875896207 ps: (kmac_edn_timeout_error_vseq.sv:68) [uvm_test_top.env.virtual_sequencer.kmac_edn_timeout_error_vseq] Check failed cfg.m_kmac_app_agent_cfg[AppKeymgr].vif.kmac_data_rsp.error == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 875896207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test kmac_long_msg_and_output has 1 failures.
  - 30.kmac_long_msg_and_output.36853567812894177190113543100041235529004323834219038902997169429449305725596
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/30.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:9055039f-01f0-490a-a083-6587e828dc63
```
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 1 failures:
- Test kmac_stress_all has 1 failures.
  - 46.kmac_stress_all.111244098267637948329411929571156614759593106020057835375741258662646531662814
    Line 1928, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/46.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 30031545581 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 30031545581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```