KMAC/MASKED Simulation Results

Tuesday June 04 2024 19:02:20 UTC

GitHub Revision: `a182fcef27`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 115716131103921631007013649731972014580281041353363476420230431751664670300928

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.422m	18.016ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.240s	60.319us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.270s	30.758us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	20.900s	1.509ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.700s	1.558ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.680s	73.113us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.270s	30.758us	20	20	100.00
		kmac_csr_aliasing	9.700s	1.558ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.760s	13.706us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.440s	49.872us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	59.041m	42.459ms	50	50	100.00
V2	burst_write	kmac_burst_write	28.721m	131.757ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	44.064m	819.211ms	49	50	98.00
		kmac_test_vectors_sha3_256	39.465m	95.545ms	50	50	100.00
		kmac_test_vectors_sha3_384	32.052m	148.945ms	49	50	98.00
		kmac_test_vectors_sha3_512	23.724m	353.974ms	49	50	98.00
		kmac_test_vectors_shake_128	1.833h	1.180s	50	50	100.00
		kmac_test_vectors_shake_256	1.678h	3.044s	50	50	100.00
		kmac_test_vectors_kmac	7.200s	267.784us	50	50	100.00
		kmac_test_vectors_kmac_xof	7.070s	202.090us	50	50	100.00
V2	sideload	kmac_sideload	8.900m	50.830ms	50	50	100.00
V2	app	kmac_app	7.147m	7.445ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.817m	62.764ms	9	10	90.00
V2	entropy_refresh	kmac_entropy_refresh	6.760m	16.577ms	50	50	100.00
V2	error	kmac_error	8.061m	36.832ms	50	50	100.00
V2	key_error	kmac_key_error	13.590s	17.421ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	55.390s	4.394ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	42.630s	534.536us	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.316m	22.768ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	37.720s	2.957ms	50	50	100.00
V2	stress_all	kmac_stress_all	42.859m	259.758ms	48	50	96.00
V2	intr_test	kmac_intr_test	0.890s	75.270us	50	50	100.00
V2	alert_test	kmac_alert_test	0.930s	53.580us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.630s	933.896us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.630s	933.896us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.240s	60.319us	5	5	100.00
		kmac_csr_rw	1.270s	30.758us	20	20	100.00
		kmac_csr_aliasing	9.700s	1.558ms	5	5	100.00
		kmac_same_csr_outstanding	2.930s	547.101us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.240s	60.319us	5	5	100.00
		kmac_csr_rw	1.270s	30.758us	20	20	100.00
		kmac_csr_aliasing	9.700s	1.558ms	5	5	100.00
		kmac_same_csr_outstanding	2.930s	547.101us	20	20	100.00
V2		TOTAL			1043	1050	99.33
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.740s	117.523us	19	20	95.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.740s	117.523us	19	20	95.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.740s	117.523us	19	20	95.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.740s	117.523us	19	20	95.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.190s	501.448us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.753m	28.504ms	5	5	100.00
		kmac_tl_intg_err	5.740s	1.006ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.740s	1.006ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	37.720s	2.957ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.422m	18.016ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	8.900m	50.830ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.740s	117.523us	19	20	95.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.753m	28.504ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.753m	28.504ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.753m	28.504ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.422m	18.016ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	37.720s	2.957ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.753m	28.504ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	7.615m	19.366ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.422m	18.016ms	50	50	100.00
V2S		TOTAL			74	75	98.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	47.396m	72.537ms	21	50	42.00
V3		TOTAL			21	50	42.00
		TOTAL			1253	1290	97.13

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	19	76.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.35	97.91	92.65	99.89	77.46	95.59	99.05	97.88

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:
- Test kmac_stress_all_with_rand_reset has 20 failures.
  - 0.kmac_stress_all_with_rand_reset.35051175469902794065885167052217196864016318065866380191850259161869197073258
    Line 2550, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 35297441586 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 35297441586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.kmac_stress_all_with_rand_reset.11757249350276109238922756144137288410014563293620127676459129920225025710954
    Line 1107, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 42669610864 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 42669610864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 18 more failures.
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 7 failures:
- Test kmac_stress_all_with_rand_reset has 7 failures.
  - 2.kmac_stress_all_with_rand_reset.39930295684002635402751740484107977017347188826300359470920966686597803625346
    Line 523, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9356614391 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483736 [0x80000058]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 9356614391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.kmac_stress_all_with_rand_reset.55858595192246268493743534883457379841747893072466840320641730846007078766533
    Line 318, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1058245241 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483768 [0x80000078]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 1058245241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 5 failures:

Test kmac_test_vectors_sha3_384 has 1 failures.

22.kmac_test_vectors_sha3_384.54892502711404436109244579710426770880381461558373616537524455326528410209413
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/22.kmac_test_vectors_sha3_384/latest/run.log

  UVM_ERROR @  87750731 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  87750731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_test_vectors_sha3_512 has 1 failures.

26.kmac_test_vectors_sha3_512.48282698799355216383621800820697004530873653686849583265303546557735360368931
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/26.kmac_test_vectors_sha3_512/latest/run.log

  UVM_ERROR @  71544380 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  71544380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_test_vectors_sha3_224 has 1 failures.

29.kmac_test_vectors_sha3_224.111618137623322658578452045572565587286261644465137086712411890370886434517814
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/29.kmac_test_vectors_sha3_224/latest/run.log

  UVM_ERROR @  38351729 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  38351729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 2 failures.

41.kmac_stress_all.38168278853113812537427599086515011228259859666419935408645691783866597138809
Line 637, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/41.kmac_stress_all/latest/run.log

  UVM_ERROR @ 12129644130 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 12129644130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

49.kmac_stress_all.63082076558488517738077103306279933171939802817288120162499426051133481937791
Line 635, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/49.kmac_stress_all/latest/run.log

  UVM_ERROR @ 8452475224 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 8452475224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 2 failures:
- Test kmac_stress_all_with_rand_reset has 2 failures.
  - 13.kmac_stress_all_with_rand_reset.21778366713155757712044651348785932355865914935954223076144636366780624486475
    Line 990, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 42838789378 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 42838789378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 22.kmac_stress_all_with_rand_reset.97908939875628516093851203664682079188134674580997530189598462012615347142536
    Line 2311, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/22.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 100985664574 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 100985664574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 1 failures:
- Test kmac_app_with_partial_data has 1 failures.
  - 8.kmac_app_with_partial_data.20890900524739138308457642151480291884068173961523011508658473003166517110758
    Line 479, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_app_with_partial_data/latest/run.log
```
  UVM_FATAL @ 21060236640 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (139 [0x8b] vs 219 [0xdb]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 21060236640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_burst_write has 1 failures.
  - 9.kmac_burst_write.11053227635377843096711471462536971836687554386856236941699113830821585943378
    Line 650, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 1 failures:
- Test kmac_shadow_reg_errors has 1 failures.
  - 15.kmac_shadow_reg_errors.30680119949705308427168334458962055957996385821257141880224723044732171046801
    Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_shadow_reg_errors/latest/run.log
```
  UVM_ERROR @  44278729 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  44278729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```