KMAC/MASKED Simulation Results

Wednesday June 05 2024 22:14:46 UTC

GitHub Revision: `b29ffbb03c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 104714960319679935410420483500971829136303708457300037460974663680452494898918

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.629m	53.855ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.170s	28.648us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.220s	29.083us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	19.110s	972.023us	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.320s	495.848us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.580s	38.000us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.220s	29.083us	20	20	100.00
		kmac_csr_aliasing	9.320s	495.848us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.770s	72.385us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.540s	79.175us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	55.062m	421.125ms	49	50	98.00
V2	burst_write	kmac_burst_write	27.647m	61.047ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	42.282m	202.503ms	50	50	100.00
		kmac_test_vectors_sha3_256	39.916m	1.319s	49	50	98.00
		kmac_test_vectors_sha3_384	32.084m	232.641ms	50	50	100.00
		kmac_test_vectors_sha3_512	25.878m	999.359ms	50	50	100.00
		kmac_test_vectors_shake_128	1.926h	3.776s	49	50	98.00
		kmac_test_vectors_shake_256	1.662h	2.460s	50	50	100.00
		kmac_test_vectors_kmac	7.030s	450.728us	50	50	100.00
		kmac_test_vectors_kmac_xof	7.150s	1.025ms	50	50	100.00
V2	sideload	kmac_sideload	9.356m	33.935ms	50	50	100.00
V2	app	kmac_app	6.644m	12.980ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.916m	56.075ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.671m	75.256ms	49	50	98.00
V2	error	kmac_error	9.282m	90.458ms	48	50	96.00
V2	key_error	kmac_key_error	13.710s	10.483ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	46.680s	2.067ms	19	20	95.00
V2	entropy_mode_error	kmac_entropy_mode_error	34.000s	809.581us	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.201m	28.502ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	42.940s	2.640ms	50	50	100.00
V2	stress_all	kmac_stress_all	51.766m	140.937ms	47	50	94.00
V2	intr_test	kmac_intr_test	0.860s	177.380us	50	50	100.00
V2	alert_test	kmac_alert_test	0.910s	268.126us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.090s	121.130us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.090s	121.130us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.170s	28.648us	5	5	100.00
		kmac_csr_rw	1.220s	29.083us	20	20	100.00
		kmac_csr_aliasing	9.320s	495.848us	5	5	100.00
		kmac_same_csr_outstanding	2.560s	120.583us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.170s	28.648us	5	5	100.00
		kmac_csr_rw	1.220s	29.083us	20	20	100.00
		kmac_csr_aliasing	9.320s	495.848us	5	5	100.00
		kmac_same_csr_outstanding	2.560s	120.583us	20	20	100.00
V2		TOTAL			1038	1050	98.86
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.270s	233.232us	15	20	75.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.270s	233.232us	15	20	75.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.270s	233.232us	15	20	75.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.270s	233.232us	15	20	75.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.950s	444.151us	17	20	85.00
V2S	tl_intg_err	kmac_sec_cm	1.860m	135.067ms	5	5	100.00
		kmac_tl_intg_err	5.590s	1.726ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.590s	1.726ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	42.940s	2.640ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.629m	53.855ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	9.356m	33.935ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.270s	233.232us	15	20	75.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.860m	135.067ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.860m	135.067ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.860m	135.067ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.629m	53.855ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	42.940s	2.640ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.860m	135.067ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.901m	37.943ms	9	10	90.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.629m	53.855ms	50	50	100.00
V2S		TOTAL			66	75	88.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.092h	108.387ms	16	50	32.00
V3		TOTAL			16	50	32.00
		TOTAL			1235	1290	95.74

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	16	64.00
V2S	5	5	2	40.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.43	97.91	92.65	99.89	78.17	95.59	99.05	97.73

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 29 failures:
- Test kmac_stress_all_with_rand_reset has 29 failures.
  - 0.kmac_stress_all_with_rand_reset.19624537304138102404166185808611078635966688018326236640615433484074146602993
    Line 1027, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 18469774159 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 18469774159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.kmac_stress_all_with_rand_reset.95028616872281234291122452457219976300740655439057403707743968396696687802662
    Line 815, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 52798216634 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 52798216634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 27 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 7 failures:

Test kmac_shadow_reg_errors has 5 failures.

1.kmac_shadow_reg_errors.77719346384823457510301330244240915954183048571861317893876333564711266523042
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @   7917547 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @   7917547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.kmac_shadow_reg_errors.10713808327916993093225100364646510375561210009663380256405221687332489965263
Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  47130811 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  47130811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test kmac_shadow_reg_errors_with_csr_rw has 2 failures.

3.kmac_shadow_reg_errors_with_csr_rw.37075390683599428319270020306604826892818122724664510895884303758782891624912
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  18780612 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  18780612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.kmac_shadow_reg_errors_with_csr_rw.51085463466869783130455515191856775674211577123384990904588844290610452613122
Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @ 275856164 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @ 275856164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 6 failures:

Test kmac_mubi has 1 failures.

1.kmac_mubi.89506307880454805824531003729073847469130158992876556918443365482767559638974
Line 1043, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_mubi/latest/run.log

  UVM_FATAL @ 9771791220 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (113 [0x71] vs 90 [0x5a]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 9771791220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 3 failures.

5.kmac_stress_all.37153888262573237784778433071043382468873251438706656589582091567243394884359
Line 591, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_stress_all/latest/run.log

  UVM_FATAL @ 2530160182 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (199 [0xc7] vs 117 [0x75]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 2530160182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

10.kmac_stress_all.70385108096616302511312800315801465269681159163736475285231646242659094324960
Line 1301, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_stress_all/latest/run.log

  UVM_FATAL @ 207038891208 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (194 [0xc2] vs 248 [0xf8]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 207038891208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test kmac_entropy_refresh has 1 failures.

14.kmac_entropy_refresh.78112464249191372871248425970793664724160690630358138707832195216811834462125
Line 801, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 12226481334 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (202 [0xca] vs 121 [0x79]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 12226481334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 1 failures.

21.kmac_app.17994301771585733122765386548647616135506776050583054808360327806106347183759
Line 669, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/21.kmac_app/latest/run.log

  UVM_FATAL @ 5793379117 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (77 [0x4d] vs 182 [0xb6]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 5793379117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 5 failures:
- Test kmac_stress_all_with_rand_reset has 5 failures.
  - 1.kmac_stress_all_with_rand_reset.106462780160497582447004663286697222044249426751694845209427730439879351080072
    Line 300, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1017295908 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483736 [0x80000058]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 1017295908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.kmac_stress_all_with_rand_reset.101040862521135456290871019445889167583298952337222362863403591581661672312022
    Line 1518, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 118906938842 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483704 [0x80000038]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 118906938842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 2 failures:
- Test kmac_test_vectors_sha3_256 has 1 failures.
  - 29.kmac_test_vectors_sha3_256.85794223132444036337316725010663199197194850229698376695554042056917136590119
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/29.kmac_test_vectors_sha3_256/latest/run.log
```
  UVM_ERROR @  84873780 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  84873780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_shake_128 has 1 failures.
  - 45.kmac_test_vectors_shake_128.50158313200073835380089477046429181141526160002910228282668034446238617207222
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/45.kmac_test_vectors_shake_128/latest/run.log
```
  UVM_ERROR @  86761812 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  86761812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test kmac_error has 1 failures.
  - 36.kmac_error.84612030021913687401665234576850043655758473019868636978603835799487307741646
    Line 862, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/36.kmac_error/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_burst_write has 1 failures.
  - 42.kmac_burst_write.71890034974578892227429550344131016584689046087935860145966931640986223227214
    Line 1304, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/42.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (kmac_edn_timeout_error_vseq.sv:68) [kmac_edn_timeout_error_vseq] Check failed cfg.m_kmac_app_agent_cfg[AppKeymgr].vif.kmac_data_rsp.error == * (* [*] vs * [*]) has 1 failures:
- Test kmac_edn_timeout_error has 1 failures.
  - 4.kmac_edn_timeout_error.81308263663569027427185675620574986222048109577620805372802171836431333176331
    Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_edn_timeout_error/latest/run.log
```
  UVM_ERROR @ 217933342 ps: (kmac_edn_timeout_error_vseq.sv:68) [uvm_test_top.env.virtual_sequencer.kmac_edn_timeout_error_vseq] Check failed cfg.m_kmac_app_agent_cfg[AppKeymgr].vif.kmac_data_rsp.error == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 217933342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test kmac_long_msg_and_output has 1 failures.
  - 19.kmac_long_msg_and_output.31999077415132768876911631194342566554402204361116354240154586247142327517311
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:12bd2a02-1793-4acb-83d5-b2bac9e2a151
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_* reset value: * has 1 failures:
- Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.
  - 19.kmac_shadow_reg_errors_with_csr_rw.53564730014537247931269358801193491964377247027526615062708057151329003171253
    Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @ 303943223 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (2913200454 [0xada3e946] vs 0 [0x0]) Regname: kmac_reg_block.prefix_6 reset value: 0x0
  UVM_INFO @ 303943223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 1 failures:
- Test kmac_error has 1 failures.
  - 42.kmac_error.28241716431614648331436925678281214124460155551123040893341068787781338226469
    Line 389, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/42.kmac_error/latest/run.log
```
  UVM_FATAL @ 10452344242 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 10452344242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```