KMAC/MASKED Simulation Results

Thursday June 06 2024 19:04:47 UTC

GitHub Revision: `32d52b8d41`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 59908589074363629542901507660786833114562191729708937078847065421241135561861

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.436m	17.368ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.160s	32.872us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.240s	32.995us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	21.710s	1.483ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	11.310s	2.149ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.640s	141.938us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.240s	32.995us	20	20	100.00
		kmac_csr_aliasing	11.310s	2.149ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.770s	89.667us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.560s	49.007us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	56.688m	391.625ms	49	50	98.00
V2	burst_write	kmac_burst_write	30.830m	15.417ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	42.709m	383.285ms	49	50	98.00
		kmac_test_vectors_sha3_256	40.108m	132.357ms	50	50	100.00
		kmac_test_vectors_sha3_384	36.267m	1.201s	50	50	100.00
		kmac_test_vectors_sha3_512	23.706m	135.281ms	50	50	100.00
		kmac_test_vectors_shake_128	1.977h	1.446s	50	50	100.00
		kmac_test_vectors_shake_256	1.571h	408.111ms	50	50	100.00
		kmac_test_vectors_kmac	7.690s	4.277ms	50	50	100.00
		kmac_test_vectors_kmac_xof	7.480s	923.379us	50	50	100.00
V2	sideload	kmac_sideload	8.595m	19.249ms	50	50	100.00
V2	app	kmac_app	7.822m	85.707ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.881m	66.233ms	9	10	90.00
V2	entropy_refresh	kmac_entropy_refresh	6.231m	17.323ms	50	50	100.00
V2	error	kmac_error	8.227m	56.153ms	50	50	100.00
V2	key_error	kmac_key_error	14.100s	1.785ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	43.200s	549.052us	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	48.250s	4.254ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.176m	7.282ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	1.014m	3.506ms	50	50	100.00
V2	stress_all	kmac_stress_all	51.350m	373.409ms	48	50	96.00
V2	intr_test	kmac_intr_test	0.880s	24.989us	50	50	100.00
V2	alert_test	kmac_alert_test	0.910s	69.967us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.450s	128.921us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.450s	128.921us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.160s	32.872us	5	5	100.00
		kmac_csr_rw	1.240s	32.995us	20	20	100.00
		kmac_csr_aliasing	11.310s	2.149ms	5	5	100.00
		kmac_same_csr_outstanding	2.720s	154.642us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.160s	32.872us	5	5	100.00
		kmac_csr_rw	1.240s	32.995us	20	20	100.00
		kmac_csr_aliasing	11.310s	2.149ms	5	5	100.00
		kmac_same_csr_outstanding	2.720s	154.642us	20	20	100.00
V2		TOTAL			1044	1050	99.43
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.340s	141.415us	15	20	75.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.340s	141.415us	15	20	75.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.340s	141.415us	15	20	75.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.340s	141.415us	15	20	75.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.050s	445.888us	19	20	95.00
V2S	tl_intg_err	kmac_sec_cm	1.879m	14.018ms	5	5	100.00
		kmac_tl_intg_err	5.820s	894.203us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.820s	894.203us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.014m	3.506ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.436m	17.368ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	8.595m	19.249ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.340s	141.415us	15	20	75.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.879m	14.018ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.879m	14.018ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.879m	14.018ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.436m	17.368ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.014m	3.506ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.879m	14.018ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.177m	8.647ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.436m	17.368ms	50	50	100.00
V2S		TOTAL			69	75	92.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	52.409m	459.508ms	13	50	26.00
V3		TOTAL			13	50	26.00
		TOTAL			1241	1290	96.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	20	80.00
V2S	5	5	3	60.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.20	97.89	92.58	99.89	76.76	95.53	98.89	97.88

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 26 failures:
- Test kmac_stress_all_with_rand_reset has 26 failures.
  - 0.kmac_stress_all_with_rand_reset.90568721483363458976937166451729638865196974263399661632967605254161571065816
    Line 1759, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 92497098594 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 92497098594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.62390062239371422765115690737321155413475633666371175564620059146007857469305
    Line 686, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 48738564926 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 48738564926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 24 more failures.
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 8 failures:
- Test kmac_stress_all_with_rand_reset has 8 failures.
  - 3.kmac_stress_all_with_rand_reset.10415378156095081988859710045690292388482997374411141485928611831338922898427
    Line 262, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 484198904 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483648 [0x80000000]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 484198904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.kmac_stress_all_with_rand_reset.14493925103968777615307248164249859754350324002953189213551609704140277315145
    Line 1994, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 112586046491 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483656 [0x80000008]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 112586046491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 6 failures:

Test kmac_shadow_reg_errors has 5 failures.

6.kmac_shadow_reg_errors.63645104572715647174289578776353776839984928798673909696321962315163507784640
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @   7872135 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @   7872135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.kmac_shadow_reg_errors.113703988977131824651691791102932195727845039360248691496376717014785697045153
Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  16873084 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  16873084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

16.kmac_shadow_reg_errors_with_csr_rw.25786423104724865880660691095931328274234439523287186737018799526274583609408
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  20885837 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  20885837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 4 failures:
- Test kmac_stress_all_with_rand_reset has 3 failures.
  - 13.kmac_stress_all_with_rand_reset.20405402315200426476265450684999700636196794252958865374691637297283714533611
    Line 2669, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 917955158147 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 917955158147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 16.kmac_stress_all_with_rand_reset.36310625437531321818730703914510723687023467445184153208851088504895238387294
    Line 3961, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 285505595168 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 285505595168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test kmac_stress_all has 1 failures.
  - 25.kmac_stress_all.11758832510693421909198944604579160194428079982986332803369493834300621444081
    Line 1514, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/25.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 66097796553 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 66097796553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 2 failures:
- Test kmac_app_with_partial_data has 1 failures.
  - 1.kmac_app_with_partial_data.78681391723281915864797345119633118072912656899896704285244092082611126799757
    Line 937, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_app_with_partial_data/latest/run.log
```
  UVM_FATAL @ 17021292056 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (245 [0xf5] vs 42 [0x2a]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 17021292056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_stress_all has 1 failures.
  - 28.kmac_stress_all.108091089343523581524842888055644511374378957410747981472656534604258030569712
    Line 957, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/28.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 26390722837 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (189 [0xbd] vs 100 [0x64]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 26390722837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 1 failures:
- Test kmac_test_vectors_sha3_224 has 1 failures.
  - 13.kmac_test_vectors_sha3_224.21586092945846488842146474882397708199185139210555828550485734507193996189246
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_test_vectors_sha3_224/latest/run.log
```
  UVM_ERROR @  25737868 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  25737868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_burst_write has 1 failures.
  - 15.kmac_burst_write.17181607862844906036210086912480755982437237612452156143713454719984116376565
    Line 573, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test kmac_long_msg_and_output has 1 failures.
  - 36.kmac_long_msg_and_output.114704371280166535578724522371580320557928362351057741897918601237761303319291
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/36.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:9a09c952-8861-4002-b7aa-b71e24313fed
```