KMAC/MASKED Simulation Results

Saturday June 08 2024 00:41:57 UTC

GitHub Revision: `302b24f3c6`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 32491226968592963393132943636196950930602503490106290691157604759716956925599

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.443m	15.508ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.200s	120.234us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.220s	32.607us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	19.330s	8.005ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.210s	4.225ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.500s	34.499us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.220s	32.607us	20	20	100.00
		kmac_csr_aliasing	10.210s	4.225ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.780s	155.309us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.490s	122.847us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	57.361m	495.637ms	50	50	100.00
V2	burst_write	kmac_burst_write	25.568m	15.115ms	47	50	94.00
V2	test_vectors	kmac_test_vectors_sha3_224	46.883m	892.101ms	50	50	100.00
		kmac_test_vectors_sha3_256	39.583m	94.569ms	50	50	100.00
		kmac_test_vectors_sha3_384	31.691m	260.134ms	49	50	98.00
		kmac_test_vectors_sha3_512	24.047m	406.383ms	49	50	98.00
		kmac_test_vectors_shake_128	1.768h	1.191s	50	50	100.00
		kmac_test_vectors_shake_256	1.824h	3.148s	50	50	100.00
		kmac_test_vectors_kmac	6.980s	1.230ms	50	50	100.00
		kmac_test_vectors_kmac_xof	7.440s	3.068ms	50	50	100.00
V2	sideload	kmac_sideload	8.431m	126.816ms	50	50	100.00
V2	app	kmac_app	7.066m	18.958ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.745m	86.344ms	9	10	90.00
V2	entropy_refresh	kmac_entropy_refresh	7.030m	35.248ms	49	50	98.00
V2	error	kmac_error	9.242m	7.904ms	49	50	98.00
V2	key_error	kmac_key_error	16.130s	10.477ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	48.630s	3.170ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	41.080s	1.301ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.054m	50.430ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	44.350s	921.938us	50	50	100.00
V2	stress_all	kmac_stress_all	54.033m	58.957ms	48	50	96.00
V2	intr_test	kmac_intr_test	0.910s	42.168us	50	50	100.00
V2	alert_test	kmac_alert_test	0.910s	16.300us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.360s	116.452us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.360s	116.452us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.200s	120.234us	5	5	100.00
		kmac_csr_rw	1.220s	32.607us	20	20	100.00
		kmac_csr_aliasing	10.210s	4.225ms	5	5	100.00
		kmac_same_csr_outstanding	2.640s	234.896us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.200s	120.234us	5	5	100.00
		kmac_csr_rw	1.220s	32.607us	20	20	100.00
		kmac_csr_aliasing	10.210s	4.225ms	5	5	100.00
		kmac_same_csr_outstanding	2.640s	234.896us	20	20	100.00
V2		TOTAL			1039	1050	98.95
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.490s	69.382us	16	20	80.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.490s	69.382us	16	20	80.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.490s	69.382us	16	20	80.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.490s	69.382us	16	20	80.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.770s	468.584us	18	20	90.00
V2S	tl_intg_err	kmac_sec_cm	1.994m	33.152ms	5	5	100.00
		kmac_tl_intg_err	5.230s	550.945us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.230s	550.945us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	44.350s	921.938us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.443m	15.508ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	8.431m	126.816ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.490s	69.382us	16	20	80.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.994m	33.152ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.994m	33.152ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.994m	33.152ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.443m	15.508ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	44.350s	921.938us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.994m	33.152ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.805m	6.096ms	9	10	90.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.443m	15.508ms	50	50	100.00
V2S		TOTAL			68	75	90.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	51.897m	291.333ms	15	50	30.00
V3		TOTAL			15	50	30.00
		TOTAL			1237	1290	95.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	17	68.00
V2S	5	5	2	40.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.15	97.91	92.65	99.89	76.06	95.59	99.05	97.88

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 28 failures:
- Test kmac_stress_all_with_rand_reset has 28 failures.
  - 0.kmac_stress_all_with_rand_reset.47188345504432982357280724116419273688366543398054241024118291147265384825216
    Line 401, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5047521430 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5047521430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.113632617947724407503418738824055115918711263405392096293358266489778468705996
    Line 1375, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 39320197580 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 39320197580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 26 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 6 failures:

Test kmac_shadow_reg_errors has 4 failures.

3.kmac_shadow_reg_errors.86188072708501710040118818287714736328821395025996497740113339897478837110328
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @ 110545720 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @ 110545720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.kmac_shadow_reg_errors.87272628622075872831124218210914679387449784421422961482744452089604723734627
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @   4932747 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @   4932747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test kmac_shadow_reg_errors_with_csr_rw has 2 failures.

5.kmac_shadow_reg_errors_with_csr_rw.102038468343095950609717717725348428984080010770842012123686944134499987770226
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @   7660920 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @   7660920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.kmac_shadow_reg_errors_with_csr_rw.69990775314870559064375980999869438054009899963441604605315069499443497445209
Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  48481452 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  48481452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 6 failures:
- Test kmac_stress_all_with_rand_reset has 6 failures.
  - 6.kmac_stress_all_with_rand_reset.44121402489463283561384067968853136102317499333453651831029271133840069086397
    Line 521, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6445565800 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483736 [0x80000058]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 6445565800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.kmac_stress_all_with_rand_reset.83193903518596686473483657841572198567149894187911432587317309864363887973349
    Line 293, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 765390027 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483664 [0x80000010]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 765390027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
- Test kmac_burst_write has 3 failures.
  - 7.kmac_burst_write.94706247546174777274168310134132676060509539532429581114349657445490599106590
    Line 711, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 34.kmac_burst_write.5458902410175951199682719476127632758478500890332984717131973737485784205477
    Line 932, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/34.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test kmac_app_with_partial_data has 1 failures.
  - 8.kmac_app_with_partial_data.23882781703011072611823002633937425527209948203945192141275776103720790810785
    Line 832, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_app_with_partial_data/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 4 failures:

Test kmac_mubi has 1 failures.

8.kmac_mubi.63307600739714515095891005955126107072059883662168672947410727890219064365253
Line 497, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_mubi/latest/run.log

  UVM_FATAL @ 6740297891 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (172 [0xac] vs 87 [0x57]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 6740297891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 1 failures.

26.kmac_app.59118942070662575109378008801880436925049828339152997777055717209861184095753
Line 553, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/26.kmac_app/latest/run.log

  UVM_FATAL @ 4359042930 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (58 [0x3a] vs 5 [0x5]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 4359042930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 1 failures.

31.kmac_entropy_refresh.25714249282114406392017755115750492711649568469202359719182950118861823268815
Line 965, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/31.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 6270247573 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (3 [0x3] vs 139 [0x8b]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 6270247573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 1 failures.

46.kmac_stress_all.55179940733635764629455606315252978598888717799536182334660114350769956410326
Line 705, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/46.kmac_stress_all/latest/run.log

  UVM_FATAL @ 9014899090 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (99 [0x63] vs 165 [0xa5]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 9014899090 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 3 failures:
- Test kmac_test_vectors_sha3_384 has 1 failures.
  - 20.kmac_test_vectors_sha3_384.46135184271874480523226005434139870124757307432266977470943057563194200724361
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/20.kmac_test_vectors_sha3_384/latest/run.log
```
  UVM_ERROR @  33511252 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  33511252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_sha3_512 has 1 failures.
  - 29.kmac_test_vectors_sha3_512.77249187716667278199327673657310402696804729057953524650982966456336624543157
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/29.kmac_test_vectors_sha3_512/latest/run.log
```
  UVM_ERROR @  24130881 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  24130881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_stress_all has 1 failures.
  - 47.kmac_stress_all.20771924771031727394289509780043295003318290985843417948482195179219967707570
    Line 1844, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/47.kmac_stress_all/latest/run.log
```
  UVM_ERROR @ 73443255379 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 73443255379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 2 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 5.kmac_stress_all_with_rand_reset.58946102331764286699711394968241823865476384613821764931528348371903880764910
    Line 720, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 19349244365 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 19349244365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_error has 1 failures.
  - 30.kmac_error.101685771976559302341693750622709606980582076558563632794564014097890744099121
    Line 672, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/30.kmac_error/latest/run.log
```
  UVM_FATAL @ 10141427281 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 10141427281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```