KMAC/MASKED Simulation Results

Monday July 01 2024 17:07:21 UTC

GitHub Revision: `eb56ef55d0`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 287373712151371957859909226915296476629077008125381265920192201371239303276

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.549m	21.525ms	49	50	98.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.100s	61.202us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.200s	110.621us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	19.470s	1.947ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.850s	2.003ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.910s	436.695us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.200s	110.621us	20	20	100.00
		kmac_csr_aliasing	9.850s	2.003ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.800s	10.768us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.520s	148.196us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	long_msg_and_output	kmac_long_msg_and_output	58.390m	655.788ms	50	50	100.00
V2	burst_write	kmac_burst_write	27.229m	24.145ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	43.789m	480.300ms	50	50	100.00
		kmac_test_vectors_sha3_256	41.634m	95.573ms	49	50	98.00
		kmac_test_vectors_sha3_384	32.599m	315.986ms	50	50	100.00
		kmac_test_vectors_sha3_512	24.152m	53.005ms	49	50	98.00
		kmac_test_vectors_shake_128	1.987h	2.017s	50	50	100.00
		kmac_test_vectors_shake_256	1.608h	1.045s	50	50	100.00
		kmac_test_vectors_kmac	8.270s	1.223ms	49	50	98.00
		kmac_test_vectors_kmac_xof	7.350s	1.325ms	50	50	100.00
V2	sideload	kmac_sideload	8.571m	14.524ms	50	50	100.00
V2	app	kmac_app	7.655m	92.818ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.894m	60.785ms	9	10	90.00
V2	entropy_refresh	kmac_entropy_refresh	7.163m	36.595ms	48	50	96.00
V2	error	kmac_error	8.706m	6.195ms	50	50	100.00
V2	key_error	kmac_key_error	21.500s	24.854ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	46.530s	2.847ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	34.160s	4.270ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.181m	13.341ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	34.810s	935.541us	50	50	100.00
V2	stress_all	kmac_stress_all	53.194m	264.791ms	46	50	92.00
V2	intr_test	kmac_intr_test	0.920s	64.196us	50	50	100.00
V2	alert_test	kmac_alert_test	0.890s	20.235us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.750s	295.484us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.750s	295.484us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.100s	61.202us	5	5	100.00
		kmac_csr_rw	1.200s	110.621us	20	20	100.00
		kmac_csr_aliasing	9.850s	2.003ms	5	5	100.00
		kmac_same_csr_outstanding	2.740s	455.112us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.100s	61.202us	5	5	100.00
		kmac_csr_rw	1.200s	110.621us	20	20	100.00
		kmac_csr_aliasing	9.850s	2.003ms	5	5	100.00
		kmac_same_csr_outstanding	2.740s	455.112us	20	20	100.00
V2		TOTAL			1038	1050	98.86
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.570s	216.273us	17	20	85.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.570s	216.273us	17	20	85.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.570s	216.273us	17	20	85.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.570s	216.273us	17	20	85.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.120s	392.755us	16	20	80.00
V2S	tl_intg_err	kmac_sec_cm	1.783m	7.946ms	5	5	100.00
		kmac_tl_intg_err	5.840s	344.665us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.840s	344.665us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	34.810s	935.541us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.549m	21.525ms	49	50	98.00
V2S	sec_cm_key_sideload	kmac_sideload	8.571m	14.524ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.570s	216.273us	17	20	85.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.783m	7.946ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.783m	7.946ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.783m	7.946ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.549m	21.525ms	49	50	98.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	34.810s	935.541us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.783m	7.946ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.286m	17.402ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.549m	21.525ms	49	50	98.00
V2S		TOTAL			68	75	90.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	31.920m	97.270ms	5	10	50.00
V3		TOTAL			5	10	50.00
		TOTAL			1225	1250	98.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	25	25	17	68.00
V2S	5	5	3	60.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.38	97.89	92.58	99.89	78.17	95.53	98.89	97.73

Failure Buckets

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 6 failures:

Test kmac_shadow_reg_errors has 3 failures.

3.kmac_shadow_reg_errors.69438753248435063633346675069822330960639282374089979303037172872777177548320
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @   4514964 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @   4514964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.kmac_shadow_reg_errors.112761211326658385233683699520680081637846410499087842511436520845159248842054
Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  36409156 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  36409156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test kmac_shadow_reg_errors_with_csr_rw has 3 failures.

9.kmac_shadow_reg_errors_with_csr_rw.110434563815774298033667914851420128537864357822728003520145626342604289067359
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  15622513 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  15622513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

12.kmac_shadow_reg_errors_with_csr_rw.82370284688878610681707458410318734847708989090066706302057110959192875360036
Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @ 259507695 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @ 259507695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 6 failures:

Test kmac_app_with_partial_data has 1 failures.

4.kmac_app_with_partial_data.19730959412642147980592017004604037989206971986253791005843792307558370476869
Line 269, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_app_with_partial_data/latest/run.log

  UVM_FATAL @ 257910903 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (7 [0x7] vs 83 [0x53]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 257910903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 1 failures.

8.kmac_entropy_refresh.1436379610475104171309852638735988185993638441955646543153851279490439380993
Line 433, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 4498576834 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (55 [0x37] vs 88 [0x58]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 4498576834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 3 failures.

8.kmac_stress_all.90659388559944300760743336665434294123235384720940357349347356444422974007379
Line 1857, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_stress_all/latest/run.log

  UVM_FATAL @ 908492082198 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (114 [0x72] vs 183 [0xb7]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 908492082198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

11.kmac_stress_all.7749912887262843112469630056187717860579736971957232413920936265972406649358
Line 605, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_stress_all/latest/run.log

  UVM_FATAL @ 21423773524 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (27 [0x1b] vs 226 [0xe2]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 21423773524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test kmac_app has 1 failures.

40.kmac_app.97006886303954219620321600352225309947365676285359372338996694291667368890877
Line 313, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/40.kmac_app/latest/run.log

  UVM_FATAL @ 2657068556 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (229 [0xe5] vs 37 [0x25]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 2657068556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 5 failures:
- Test kmac_entropy_refresh has 1 failures.
  - 0.kmac_entropy_refresh.97124731359123111319749965223905865366706494271330864731680849533671164696745
    Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_entropy_refresh/latest/run.log
```
  UVM_ERROR @  62487737 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  62487737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_smoke has 1 failures.
  - 5.kmac_smoke.34178424997204092071151785556445783462125491964196375731248940090337801958080
    Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_smoke/latest/run.log
```
  UVM_ERROR @  90106805 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  90106805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_sha3_256 has 1 failures.
  - 7.kmac_test_vectors_sha3_256.3296733450880299441001483203680219283275721025769152380326021750291425328597
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_test_vectors_sha3_256/latest/run.log
```
  UVM_ERROR @  41281964 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  41281964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_kmac has 1 failures.
  - 12.kmac_test_vectors_kmac.39685282117945804238537788658506483263637387389761931312978082327301549507417
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_test_vectors_kmac/latest/run.log
```
  UVM_ERROR @  79493396 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  79493396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_sha3_512 has 1 failures.
  - 45.kmac_test_vectors_sha3_512.101780826217381321646055997767800486084482134335514552456100014676438745849340
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/45.kmac_test_vectors_sha3_512/latest/run.log
```
  UVM_ERROR @ 105941716 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 105941716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:828) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 5 failures:
- Test kmac_stress_all_with_rand_reset has 5 failures.
  - 2.kmac_stress_all_with_rand_reset.51491723264938054175879822281314513715304819758364565230693565006926419086418
    Line 850, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 55039298196 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 55039298196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.kmac_stress_all_with_rand_reset.36124304139526974694012525485308382155670897961707157353094223552240990475730
    Line 270, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1285410296 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1285410296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_* reset value: * has 1 failures:
- Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.
  - 6.kmac_shadow_reg_errors_with_csr_rw.27971751757140865292832342069988488454047160085795712734722330666184731889899
    Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @   2146824 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (3530726966 [0xd2729e36] vs 0 [0x0]) Regname: kmac_reg_block.prefix_8 reset value: 0x0
  UVM_INFO @   2146824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 1 failures:
- Test kmac_stress_all has 1 failures.
  - 18.kmac_stress_all.59524436394925610307848664590635781674920629031372201210611591464956074631570
    Line 2080, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 314346623343 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 314346623343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_burst_write has 1 failures.
  - 48.kmac_burst_write.49244066620411118480875267155431888920048860272760459817975470820433190618311
    Line 1010, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/48.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```