KMAC/UNMASKED Simulation Results

Sunday March 17 2024 19:02:52 UTC

GitHub Revision: c187a82ee8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 28440605375541353837496064678278045899395893237469128852560697715229879921060

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.342m	51.547ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.140s	108.302us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.180s	301.454us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	15.090s	286.820us	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.480s	4.811ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.610s	108.091us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.180s	301.454us	20	20	100.00
		kmac_csr_aliasing	10.480s	4.811ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.750s	21.814us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.490s	76.336us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	48.785m	98.666ms	50	50	100.00
V2	burst_write	kmac_burst_write	14.518m	84.201ms	48	50	96.00
V2	test_vectors	kmac_test_vectors_sha3_224	37.061m	562.188ms	50	50	100.00
		kmac_test_vectors_sha3_256	32.603m	97.476ms	50	50	100.00
		kmac_test_vectors_sha3_384	25.272m	99.103ms	50	50	100.00
		kmac_test_vectors_sha3_512	19.962m	603.712ms	50	50	100.00
		kmac_test_vectors_shake_128	1.696h	3.672s	50	50	100.00
		kmac_test_vectors_shake_256	1.370h	298.048ms	50	50	100.00
		kmac_test_vectors_kmac	5.490s	2.691ms	50	50	100.00
		kmac_test_vectors_kmac_xof	5.490s	257.723us	50	50	100.00
V2	sideload	kmac_sideload	6.863m	102.708ms	50	50	100.00
V2	app	kmac_app	5.812m	37.786ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.053m	80.339ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.866m	27.777ms	50	50	100.00
V2	error	kmac_error	6.543m	30.906ms	50	50	100.00
V2	key_error	kmac_key_error	6.450s	4.116ms	49	50	98.00
V2	edn_timeout_error	kmac_edn_timeout_error	40.000s	22.852ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	42.390s	2.221ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.004m	27.887ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	44.530s	4.080ms	50	50	100.00
V2	stress_all	kmac_stress_all	53.152m	102.652ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.870s	36.065us	50	50	100.00
V2	alert_test	kmac_alert_test	0.900s	106.883us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.910s	234.425us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.910s	234.425us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.140s	108.302us	5	5	100.00
		kmac_csr_rw	1.180s	301.454us	20	20	100.00
		kmac_csr_aliasing	10.480s	4.811ms	5	5	100.00
		kmac_same_csr_outstanding	2.560s	400.439us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.140s	108.302us	5	5	100.00
		kmac_csr_rw	1.180s	301.454us	20	20	100.00
		kmac_csr_aliasing	10.480s	4.811ms	5	5	100.00
		kmac_same_csr_outstanding	2.560s	400.439us	20	20	100.00
V2		TOTAL			1047	1050	99.71
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.410s	56.376us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.410s	56.376us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.410s	56.376us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.410s	56.376us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.020s	143.254us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.232m	5.070ms	5	5	100.00
		kmac_tl_intg_err	5.030s	412.224us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.030s	412.224us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	44.530s	4.080ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.342m	51.547ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	6.863m	102.708ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.410s	56.376us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.232m	5.070ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.232m	5.070ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.232m	5.070ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.342m	51.547ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	44.530s	4.080ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.232m	5.070ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.832m	59.317ms	9	10	90.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.342m	51.547ms	50	50	100.00
V2S		TOTAL			74	75	98.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	37.332m	105.652ms	4	50	8.00
V3		TOTAL			4	50	8.00
		TOTAL			1240	1290	96.12

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	23	92.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.47	96.18	92.38	100.00	89.77	94.52	98.84	96.60

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:827) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 43 failures:

  • Test kmac_stress_all_with_rand_reset has 43 failures.

    • 0.kmac_stress_all_with_rand_reset.83741954153671630459810676113182298594341465555207576532033484520520076805142
      Line 813, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4743051068 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 4743051068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.kmac_stress_all_with_rand_reset.95696544661556951588030885848645155316064902777629569304973358137673989918319
      Line 1772, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 38658334671 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 38658334671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 41 more failures.

• UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 3 failures:

  • Test kmac_stress_all_with_rand_reset has 3 failures.

    • 10.kmac_stress_all_with_rand_reset.20046501653700763646381986100536237930246938445689137305193378426440418871854
      Line 535, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/10.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 28105294543 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483664 [0x80000010]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 28105294543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 22.kmac_stress_all_with_rand_reset.49268674787658463980743739284309397335526598240126263607399096208866715666158
      Line 533, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/22.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 36937894917 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483648 [0x80000000]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 36937894917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:

  • Test kmac_burst_write has 2 failures.

    • 19.kmac_burst_write.79349449840930752932211029478271427771612714459249483627646372991181021570277
      Line 782, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/19.kmac_burst_write/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 47.kmac_burst_write.67733074412606167968208694896760115725912477924398793647118442844072779795564
      Line 578, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/47.kmac_burst_write/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 1 failures:

  • Test kmac_mubi has 1 failures.

    • 0.kmac_mubi.52896749674008969188966412603637960640847538155367714299709003811500872113817
      Line 619, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_mubi/latest/run.log

        UVM_FATAL @ 8327521273 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (123 [0x7b] vs 28 [0x1c]) Mismatch between unmasked_digest[0] and dpi_digest[0]
        UVM_INFO @ 8327521273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (kmac_base_vseq.sv:383) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set! has 1 failures:

  • Test kmac_key_error has 1 failures.

    • 2.kmac_key_error.28750840902524460133209612818315271583294166844247693922800959713118927540768
      Line 281, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_key_error/latest/run.log

        UVM_ERROR @ 3530382361 ps: (kmac_base_vseq.sv:383) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
        UVM_INFO @ 3530382361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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