KMAC/UNMASKED Simulation Results

Tuesday March 19 2024 19:02:40 UTC

GitHub Revision: `f7fc348358`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 93166527750821992054916907919379261408154533955814283538537589225972237641118

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.068m	33.530ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.080s	26.103us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.180s	51.568us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	19.880s	1.487ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.090s	1.010ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.580s	75.957us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.180s	51.568us	20	20	100.00
		kmac_csr_aliasing	10.090s	1.010ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.730s	10.066us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.460s	42.522us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	50.231m	1.689s	50	50	100.00
V2	burst_write	kmac_burst_write	14.197m	108.049ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	38.172m	1.279s	50	50	100.00
		kmac_test_vectors_sha3_256	35.565m	1.199s	50	50	100.00
		kmac_test_vectors_sha3_384	26.826m	1.024s	50	50	100.00
		kmac_test_vectors_sha3_512	17.804m	203.181ms	50	50	100.00
		kmac_test_vectors_shake_128	1.644h	1.220s	50	50	100.00
		kmac_test_vectors_shake_256	1.325h	431.053ms	50	50	100.00
		kmac_test_vectors_kmac	5.980s	2.264ms	50	50	100.00
		kmac_test_vectors_kmac_xof	5.680s	927.167us	50	50	100.00
V2	sideload	kmac_sideload	7.797m	134.028ms	49	50	98.00
V2	app	kmac_app	5.469m	13.365ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.562m	12.831ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.133m	33.039ms	47	50	94.00
V2	error	kmac_error	6.548m	26.501ms	50	50	100.00
V2	key_error	kmac_key_error	6.620s	1.220ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	40.370s	3.707ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	38.070s	1.588ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.238m	33.751ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	29.400s	1.799ms	50	50	100.00
V2	stress_all	kmac_stress_all	30.788m	695.440ms	49	50	98.00
V2	intr_test	kmac_intr_test	0.830s	125.637us	50	50	100.00
V2	alert_test	kmac_alert_test	0.890s	97.471us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.940s	526.628us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.940s	526.628us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.080s	26.103us	5	5	100.00
		kmac_csr_rw	1.180s	51.568us	20	20	100.00
		kmac_csr_aliasing	10.090s	1.010ms	5	5	100.00
		kmac_same_csr_outstanding	2.690s	161.332us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.080s	26.103us	5	5	100.00
		kmac_csr_rw	1.180s	51.568us	20	20	100.00
		kmac_csr_aliasing	10.090s	1.010ms	5	5	100.00
		kmac_same_csr_outstanding	2.690s	161.332us	20	20	100.00
V2		TOTAL			1043	1050	99.33
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.430s	112.558us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.430s	112.558us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.430s	112.558us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.430s	112.558us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.380s	139.028us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	54.420s	6.404ms	5	5	100.00
		kmac_tl_intg_err	4.890s	833.273us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.890s	833.273us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	29.400s	1.799ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.068m	33.530ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.797m	134.028ms	49	50	98.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.430s	112.558us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	54.420s	6.404ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	54.420s	6.404ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	54.420s	6.404ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.068m	33.530ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	29.400s	1.799ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	54.420s	6.404ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.360m	53.184ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.068m	33.530ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	41.431m	323.228ms	5	50	10.00
V3		TOTAL			5	50	10.00
		TOTAL			1238	1290	95.97

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	20	80.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.31	96.18	92.42	100.00	88.64	94.52	98.84	96.60

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:827) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 37 failures:
- Test kmac_stress_all_with_rand_reset has 37 failures.
  - 0.kmac_stress_all_with_rand_reset.82899408303046862007617613605244264520700327591699332395224393280891226179239
    Line 336, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 19362416663 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 19362416663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.94695524709918257553180606219612409432042301746120160486335220038047825882187
    Line 501, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 32622157386 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 32622157386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 35 more failures.
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 7 failures:
- Test kmac_stress_all_with_rand_reset has 7 failures.
  - 13.kmac_stress_all_with_rand_reset.66829850007969319042409879201209572041677706438920369200401234975468675208819
    Line 495, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/13.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6287349495 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483768 [0x80000078]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 6287349495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 23.kmac_stress_all_with_rand_reset.42618024774827881962465647945551987808501891464950557578984886244015585493831
    Line 318, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/23.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1304955761 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483680 [0x80000020]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 1304955761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 5 failures:

Test kmac_app has 1 failures.

11.kmac_app.36309542645117442787218182847468704263391089480501934850045009345425613179653
Line 513, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_app/latest/run.log

  UVM_FATAL @ 16296257811 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (90 [0x5a] vs 131 [0x83]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 16296257811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 1 failures.

25.kmac_stress_all.96912868211627872021874144709455125858335556099333348607396116686995568941967
Line 399, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/25.kmac_stress_all/latest/run.log

  UVM_FATAL @ 2253381213 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (244 [0xf4] vs 169 [0xa9]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 2253381213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 2 failures.

32.kmac_entropy_refresh.28188142859577047639781058216831198837216896934869794660741212513915263978796
Line 715, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/32.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 31174367188 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (145 [0x91] vs 42 [0x2a]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 31174367188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

36.kmac_entropy_refresh.32266266556613160078751778125232188558106127923184050708968406359106616495482
Line 355, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/36.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 2005766596 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (104 [0x68] vs 180 [0xb4]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 2005766596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all_with_rand_reset has 1 failures.

48.kmac_stress_all_with_rand_reset.86096242865594051078222097018218080637360527330993504208044070310206549118525
Line 1329, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/48.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 265681320793 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (68 [0x44] vs 6 [0x6]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 265681320793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
- Test kmac_burst_write has 1 failures.
  - 24.kmac_burst_write.37249011635649466265854796605720697177960346438183229456862207732616768369403
    Line 620, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/24.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_sideload has 1 failures.
  - 31.kmac_sideload.82653990924064492386430061065977292527913141111132606738512676365695036846570
    Line 1227, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/31.kmac_sideload/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_entropy_refresh has 1 failures.
  - 41.kmac_entropy_refresh.90228928806857591466103918720822956759843252923504811953363520057857964482366
    Line 868, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/41.kmac_entropy_refresh/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```