KMAC/UNMASKED Simulation Results

Thursday March 21 2024 19:02:46 UTC

GitHub Revision: e3ca274e77

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 110450978848188291656921294920309436568649534904994074551053469482156204817270

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.216m	16.478ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.200s	128.252us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.190s	87.700us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	21.940s	1.506ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.660s	526.005us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.670s	88.647us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.190s	87.700us	20	20	100.00
		kmac_csr_aliasing	10.660s	526.005us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.740s	13.893us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.450s	37.113us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	48.694m	244.683ms	50	50	100.00
V2	burst_write	kmac_burst_write	16.085m	161.088ms	48	50	96.00
V2	test_vectors	kmac_test_vectors_sha3_224	37.918m	656.322ms	50	50	100.00
		kmac_test_vectors_sha3_256	34.400m	1.541s	50	50	100.00
		kmac_test_vectors_sha3_384	25.226m	279.450ms	50	50	100.00
		kmac_test_vectors_sha3_512	17.949m	201.741ms	50	50	100.00
		kmac_test_vectors_shake_128	1.623h	1.177s	50	50	100.00
		kmac_test_vectors_shake_256	1.335h	909.224ms	50	50	100.00
		kmac_test_vectors_kmac	5.290s	1.865ms	50	50	100.00
		kmac_test_vectors_kmac_xof	6.010s	3.559ms	50	50	100.00
V2	sideload	kmac_sideload	7.180m	78.255ms	49	50	98.00
V2	app	kmac_app	5.337m	49.320ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.349m	33.175ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.124m	38.516ms	49	50	98.00
V2	error	kmac_error	6.886m	34.822ms	50	50	100.00
V2	key_error	kmac_key_error	7.490s	6.030ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	38.190s	5.105ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	43.610s	5.952ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	42.490s	4.866ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	25.740s	626.866us	50	50	100.00
V2	stress_all	kmac_stress_all	45.004m	61.663ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.850s	50.142us	50	50	100.00
V2	alert_test	kmac_alert_test	0.850s	18.186us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.950s	107.180us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.950s	107.180us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.200s	128.252us	5	5	100.00
		kmac_csr_rw	1.190s	87.700us	20	20	100.00
		kmac_csr_aliasing	10.660s	526.005us	5	5	100.00
		kmac_same_csr_outstanding	2.560s	364.509us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.200s	128.252us	5	5	100.00
		kmac_csr_rw	1.190s	87.700us	20	20	100.00
		kmac_csr_aliasing	10.660s	526.005us	5	5	100.00
		kmac_same_csr_outstanding	2.560s	364.509us	20	20	100.00
V2		TOTAL			1046	1050	99.62
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.560s	200.439us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.560s	200.439us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.560s	200.439us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.560s	200.439us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.020s	457.560us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.365m	19.708ms	5	5	100.00
		kmac_tl_intg_err	4.680s	189.896us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.680s	189.896us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	25.740s	626.866us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.216m	16.478ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.180m	78.255ms	49	50	98.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.560s	200.439us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.365m	19.708ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.365m	19.708ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.365m	19.708ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.216m	16.478ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	25.740s	626.866us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.365m	19.708ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.389m	76.647ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.216m	16.478ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	58.910m	629.651ms	7	50	14.00
V3		TOTAL			7	50	14.00
		TOTAL			1243	1290	96.36

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	22	88.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.23	96.12	92.27	100.00	88.64	94.44	98.84	96.31

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 39 failures:

  • Test kmac_stress_all_with_rand_reset has 39 failures.

    • 0.kmac_stress_all_with_rand_reset.36521242221518230025550052011510705921087375614499637923674704054504182676518
      Line 624, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 18569388808 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 18569388808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.kmac_stress_all_with_rand_reset.57260086129195376986673907868169037516272115667627512700383171266683169851331
      Line 3042, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 242242396542 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 242242396542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 37 more failures.

• UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 4 failures:

  • Test kmac_stress_all_with_rand_reset has 4 failures.

    • 5.kmac_stress_all_with_rand_reset.13047892164380730731409846242584082135534195568477234460653907139192903500129
      Line 304, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 306266939 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483680 [0x80000020]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 306266939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 8.kmac_stress_all_with_rand_reset.33911902261944842041015900350239904364967753483597244042298863027927411823660
      Line 1699, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 159211708471 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483744 [0x80000060]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 159211708471 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 2 more failures.

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:

  • Test kmac_sideload has 1 failures.

    • 2.kmac_sideload.91775243642113404773700704033864482701292374950705696316970026851151485494319
      Line 885, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_sideload/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test kmac_burst_write has 2 failures.

    • 17.kmac_burst_write.70805087117647600191503343817335103549852972692849362994429167509251578269631
      Line 908, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/17.kmac_burst_write/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 24.kmac_burst_write.100829237674772293403257334401630367370256772273383170653434181201929375452264
      Line 818, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/24.kmac_burst_write/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 1 failures:

  • Test kmac_entropy_refresh has 1 failures.

    • 28.kmac_entropy_refresh.65755189472353498112013471286902693674396690393855338317782996269014438676853
      Line 385, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/28.kmac_entropy_refresh/latest/run.log

        UVM_FATAL @ 7054504080 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (195 [0xc3] vs 238 [0xee]) Mismatch between unmasked_digest[0] and dpi_digest[0]
        UVM_INFO @ 7054504080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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