KMAC/UNMASKED Simulation Results

Thursday June 27 2024 23:02:31 UTC

GitHub Revision: `8db2a18db1`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 100513533386727882033709335126269317053614297947080434367729937568368619502352

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.117m	17.179ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.260s	27.469us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.250s	147.012us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	20.190s	1.457ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.170s	952.606us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.840s	151.997us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.250s	147.012us	20	20	100.00
		kmac_csr_aliasing	9.170s	952.606us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.770s	11.116us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.500s	141.920us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	48.243m	127.259ms	50	50	100.00
V2	burst_write	kmac_burst_write	13.574m	65.494ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	37.600m	1.586s	50	50	100.00
		kmac_test_vectors_sha3_256	33.600m	344.285ms	50	50	100.00
		kmac_test_vectors_sha3_384	24.026m	251.248ms	50	50	100.00
		kmac_test_vectors_sha3_512	17.027m	276.114ms	50	50	100.00
		kmac_test_vectors_shake_128	1.627h	3.193s	50	50	100.00
		kmac_test_vectors_shake_256	1.251h	1.154s	50	50	100.00
		kmac_test_vectors_kmac	6.220s	4.941ms	50	50	100.00
		kmac_test_vectors_kmac_xof	6.880s	5.018ms	50	50	100.00
V2	sideload	kmac_sideload	6.932m	57.819ms	50	50	100.00
V2	app	kmac_app	5.193m	12.209ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.824m	61.157ms	9	10	90.00
V2	entropy_refresh	kmac_entropy_refresh	5.989m	15.260ms	49	50	98.00
V2	error	kmac_error	7.082m	81.475ms	48	50	96.00
V2	key_error	kmac_key_error	9.560s	2.070ms	49	50	98.00
V2	edn_timeout_error	kmac_edn_timeout_error	37.200s	503.251us	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	37.900s	2.347ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.034m	20.843ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	35.140s	6.666ms	50	50	100.00
V2	stress_all	kmac_stress_all	36.009m	98.047ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.820s	175.525us	50	50	100.00
V2	alert_test	kmac_alert_test	0.910s	245.397us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.820s	167.853us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.820s	167.853us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.260s	27.469us	5	5	100.00
		kmac_csr_rw	1.250s	147.012us	20	20	100.00
		kmac_csr_aliasing	9.170s	952.606us	5	5	100.00
		kmac_same_csr_outstanding	2.790s	677.229us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.260s	27.469us	5	5	100.00
		kmac_csr_rw	1.250s	147.012us	20	20	100.00
		kmac_csr_aliasing	9.170s	952.606us	5	5	100.00
		kmac_same_csr_outstanding	2.790s	677.229us	20	20	100.00
V2		TOTAL			1044	1050	99.43
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.350s	155.458us	18	20	90.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.350s	155.458us	18	20	90.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.350s	155.458us	18	20	90.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.350s	155.458us	18	20	90.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.080s	705.614us	16	20	80.00
V2S	tl_intg_err	kmac_sec_cm	1.100m	5.118ms	5	5	100.00
		kmac_tl_intg_err	5.800s	2.025ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.800s	2.025ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	35.140s	6.666ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.117m	17.179ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	6.932m	57.819ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.350s	155.458us	18	20	90.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.100m	5.118ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.100m	5.118ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.100m	5.118ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.117m	17.179ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	35.140s	6.666ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.100m	5.118ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.950m	20.449ms	9	10	90.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.117m	17.179ms	50	50	100.00
V2S		TOTAL			68	75	90.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	31.675m	130.040ms	4	10	40.00
V3		TOTAL			4	10	40.00
		TOTAL			1231	1250	98.48

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	20	80.00
V2S	5	5	2	40.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
91.64	95.89	92.30	100.00	63.64	94.11	98.84	96.72

Failure Buckets

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 6 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 4 failures.

0.kmac_shadow_reg_errors_with_csr_rw.110887783645496614011380037177613579109728403027954866799309713930270438321384
Line 265, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @ 246394132 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @ 246394132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.kmac_shadow_reg_errors_with_csr_rw.79649321333206430216719316213357492284282097700062672687138093434399673224951
Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @   5771584 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @   5771584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test kmac_shadow_reg_errors has 2 failures.

2.kmac_shadow_reg_errors.111976137568296790510850442776852536181647078835399244652966186799783281322633
Line 265, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  48921359 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  48921359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.kmac_shadow_reg_errors.96322790086478534937061455711404958438370508894090628379074483109963085391638
Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  67202690 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  67202690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:828) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 5 failures:
- Test kmac_stress_all_with_rand_reset has 5 failures.
  - 1.kmac_stress_all_with_rand_reset.109115496652794195111090324201463157151649450736547221789574853912799038928611
    Line 279, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5337476844 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5337476844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.kmac_stress_all_with_rand_reset.66277402457479267613016639714846015621224058705288675358492407408336233485722
    Line 506, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2038725428 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2038725428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 3 failures:

Test kmac_mubi has 1 failures.

5.kmac_mubi.10887082867121493417918973896844558429099611993685151370921205045643069267376
Line 467, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_mubi/latest/run.log

  UVM_FATAL @ 2419660165 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (151 [0x97] vs 196 [0xc4]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 2419660165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 1 failures.

6.kmac_entropy_refresh.26417653982871043173370073244358129231357816510678805394303057158788904460499
Line 687, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 35561175596 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (252 [0xfc] vs 98 [0x62]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 35561175596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app_with_partial_data has 1 failures.

8.kmac_app_with_partial_data.9115452537007097912396015959218321170828547104482104314295888657654921773417
Line 441, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_app_with_partial_data/latest/run.log

  UVM_FATAL @ 1162611113 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (39 [0x27] vs 83 [0x53]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 1162611113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
- Test kmac_error has 2 failures.
  - 9.kmac_error.11090546693664129619147322413064214989544929172746663745043858325571585569290
    Line 1006, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_error/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 35.kmac_error.72722265258485985866148438354297699496059960558392022002638957206556936400795
    Line 1087, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/35.kmac_error/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_burst_write has 1 failures.
  - 42.kmac_burst_write.18017930871237300463478770942699191133794827034205573851007275733947901874452
    Line 1071, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/42.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 0.kmac_stress_all_with_rand_reset.93489043836434733082505921013820890745065102849187480090936145651944193339656
    Line 504, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 21194285360 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483704 [0x80000038]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 21194285360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.err_code reset value: * has 1 failures:
- Test kmac_key_error has 1 failures.
  - 21.kmac_key_error.46577297013831409608654628009974128533901942537792739386509669937373854567258
    Line 251, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/21.kmac_key_error/latest/run.log
```
  UVM_ERROR @ 106636919 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 16777216 [0x1000000]) Regname: kmac_reg_block.err_code reset value: 0x0
  UVM_INFO @ 106636919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```