KMAC/UNMASKED Simulation Results

Sunday July 14 2024 23:02:31 UTC

GitHub Revision: `c04cc5d074`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 63544391231451201456762274895161998707503467555380647510071702152169450996489

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.376m	51.100ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.050s	54.399us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.210s	145.621us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	20.190s	3.857ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.500s	1.736ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.440s	315.285us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.210s	145.621us	20	20	100.00
		kmac_csr_aliasing	9.500s	1.736ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.750s	15.621us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.580s	413.992us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	50.112m	864.317ms	50	50	100.00
V2	burst_write	kmac_burst_write	14.598m	37.445ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	35.512m	412.170ms	50	50	100.00
		kmac_test_vectors_sha3_256	37.644m	1.577s	50	50	100.00
		kmac_test_vectors_sha3_384	25.442m	296.218ms	50	50	100.00
		kmac_test_vectors_sha3_512	17.961m	205.695ms	50	50	100.00
		kmac_test_vectors_shake_128	1.579h	4.261s	50	50	100.00
		kmac_test_vectors_shake_256	1.328h	1.543s	50	50	100.00
		kmac_test_vectors_kmac	5.680s	514.410us	50	50	100.00
		kmac_test_vectors_kmac_xof	5.400s	2.009ms	50	50	100.00
V2	sideload	kmac_sideload	7.098m	150.257ms	50	50	100.00
V2	app	kmac_app	5.775m	18.977ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.787m	7.514ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.372m	83.776ms	50	50	100.00
V2	error	kmac_error	7.653m	68.823ms	50	50	100.00
V2	key_error	kmac_key_error	10.550s	2.112ms	49	50	98.00
V2	edn_timeout_error	kmac_edn_timeout_error	37.510s	5.684ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	40.230s	4.120ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.251m	17.770ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	26.370s	1.376ms	50	50	100.00
V2	stress_all	kmac_stress_all	37.034m	363.445ms	48	50	96.00
V2	intr_test	kmac_intr_test	0.820s	21.914us	50	50	100.00
V2	alert_test	kmac_alert_test	0.900s	77.816us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.270s	569.243us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.270s	569.243us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.050s	54.399us	5	5	100.00
		kmac_csr_rw	1.210s	145.621us	20	20	100.00
		kmac_csr_aliasing	9.500s	1.736ms	5	5	100.00
		kmac_same_csr_outstanding	2.560s	208.800us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.050s	54.399us	5	5	100.00
		kmac_csr_rw	1.210s	145.621us	20	20	100.00
		kmac_csr_aliasing	9.500s	1.736ms	5	5	100.00
		kmac_same_csr_outstanding	2.560s	208.800us	20	20	100.00
V2		TOTAL			1046	1050	99.62
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.440s	55.772us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.440s	55.772us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.440s	55.772us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.440s	55.772us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.870s	508.233us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.054m	16.716ms	5	5	100.00
		kmac_tl_intg_err	5.420s	814.016us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.420s	814.016us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	26.370s	1.376ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.376m	51.100ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.098m	150.257ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.440s	55.772us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.054m	16.716ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.054m	16.716ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.054m	16.716ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.376m	51.100ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	26.370s	1.376ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.054m	16.716ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	3.987m	19.549ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.376m	51.100ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	27.565m	200.237ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1236	1250	98.88

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	22	88.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
91.88	95.77	90.51	100.00	67.77	93.67	98.84	96.58

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 8 failures:
- Test kmac_stress_all_with_rand_reset has 8 failures.
  - 2.kmac_stress_all_with_rand_reset.74426851630770120273633538919706452169396824638235123919058849595585810507214
    Line 288, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1961372788 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1961372788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.kmac_stress_all_with_rand_reset.55602679088893231601837052976572561899370717355413692865177480750551831782452
    Line 1275, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 240692557416 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 240692557416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 2 failures:
- Test kmac_stress_all_with_rand_reset has 2 failures.
  - 0.kmac_stress_all_with_rand_reset.106695285419124774821694278732959472114987936407431153684368482608072449637830
    Line 783, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 125320651400 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483728 [0x80000050]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 125320651400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.49584077860525692056959088069300145596720153807943685422569734909185629698182
    Line 1052, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10365664761 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483728 [0x80000050]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 10365664761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 2 failures:

Test kmac_stress_all has 2 failures.

8.kmac_stress_all.83404496680741536027497406932517434418568050385324356688589596574166824161826
Line 1183, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_stress_all/latest/run.log

  UVM_FATAL @ 39985684390 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (142 [0x8e] vs 66 [0x42]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 39985684390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

47.kmac_stress_all.36816410082317257060003403232755862847343389210735331867362237302523855680795
Line 413, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/47.kmac_stress_all/latest/run.log

  UVM_FATAL @ 9423477039 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (69 [0x45] vs 196 [0xc4]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 9423477039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.err_code reset value: * has 1 failures:
- Test kmac_key_error has 1 failures.
  - 18.kmac_key_error.10367725932418820753022879597884406329079473332414481289527234140191788380062
    Line 251, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/18.kmac_key_error/latest/run.log
```
  UVM_ERROR @  71861514 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 16777216 [0x1000000]) Regname: kmac_reg_block.err_code reset value: 0x0
  UVM_INFO @  71861514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_burst_write has 1 failures.
  - 28.kmac_burst_write.21339687745496319550319276602950175247769319119383287658196411909583010277913
    Line 956, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/28.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```