KMAC/UNMASKED Simulation Results

Monday July 15 2024 23:02:37 UTC

GitHub Revision: `a04e34f557`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 78455839157994684327892029952813991699715169368132023215715425571513813941951

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.149m	3.647ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.140s	435.354us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.150s	173.186us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	18.610s	967.679us	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.100s	2.287ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.770s	709.140us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.150s	173.186us	20	20	100.00
		kmac_csr_aliasing	10.100s	2.287ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.720s	11.699us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.430s	162.041us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	43.946m	354.677ms	50	50	100.00
V2	burst_write	kmac_burst_write	15.394m	77.456ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	35.758m	821.340ms	50	50	100.00
		kmac_test_vectors_sha3_256	33.791m	354.858ms	50	50	100.00
		kmac_test_vectors_sha3_384	30.591m	1.017s	50	50	100.00
		kmac_test_vectors_sha3_512	17.329m	48.555ms	50	50	100.00
		kmac_test_vectors_shake_128	1.500h	852.898ms	50	50	100.00
		kmac_test_vectors_shake_256	1.302h	2.424s	50	50	100.00
		kmac_test_vectors_kmac	5.660s	971.526us	50	50	100.00
		kmac_test_vectors_kmac_xof	6.100s	3.426ms	50	50	100.00
V2	sideload	kmac_sideload	8.003m	128.400ms	50	50	100.00
V2	app	kmac_app	5.322m	54.467ms	48	50	96.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.862m	16.318ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.641m	21.206ms	48	50	96.00
V2	error	kmac_error	6.194m	20.679ms	50	50	100.00
V2	key_error	kmac_key_error	13.620s	16.645ms	48	50	96.00
V2	edn_timeout_error	kmac_edn_timeout_error	38.570s	7.483ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	45.090s	2.279ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	53.930s	25.479ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	1.085m	962.242us	50	50	100.00
V2	stress_all	kmac_stress_all	36.270m	26.860ms	49	50	98.00
V2	intr_test	kmac_intr_test	0.840s	48.573us	50	50	100.00
V2	alert_test	kmac_alert_test	0.910s	274.136us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.730s	2.417ms	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.730s	2.417ms	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.140s	435.354us	5	5	100.00
		kmac_csr_rw	1.150s	173.186us	20	20	100.00
		kmac_csr_aliasing	10.100s	2.287ms	5	5	100.00
		kmac_same_csr_outstanding	2.540s	2.069ms	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.140s	435.354us	5	5	100.00
		kmac_csr_rw	1.150s	173.186us	20	20	100.00
		kmac_csr_aliasing	10.100s	2.287ms	5	5	100.00
		kmac_same_csr_outstanding	2.540s	2.069ms	20	20	100.00
V2		TOTAL			1042	1050	99.24
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.390s	56.589us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.390s	56.589us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.390s	56.589us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.390s	56.589us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.910s	144.290us	19	20	95.00
V2S	tl_intg_err	kmac_sec_cm	42.890s	6.235ms	5	5	100.00
		kmac_tl_intg_err	5.400s	485.453us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.400s	485.453us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.085m	962.242us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.149m	3.647ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	8.003m	128.400ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.390s	56.589us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	42.890s	6.235ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	42.890s	6.235ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	42.890s	6.235ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.149m	3.647ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.085m	962.242us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	42.890s	6.235ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.304m	67.161ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.149m	3.647ms	50	50	100.00
V2S		TOTAL			74	75	98.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	25.540m	394.732ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1231	1250	98.48

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	20	80.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
91.78	95.77	90.51	100.00	66.94	93.67	98.84	96.72

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 6 failures:
- Test kmac_stress_all_with_rand_reset has 6 failures.
  - 0.kmac_stress_all_with_rand_reset.100138699350695454802666009619698080548091229638135583432957247009773237358785
    Line 1252, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 38576594135 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 38576594135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.18812554096946877273417263126391673016684224004589427287959475766871330508991
    Line 403, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8200108862 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 8200108862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 5 failures:

Test kmac_app has 2 failures.

13.kmac_app.35411427018242346028088315025973114313087830248407412048917983806954830538686
Line 939, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/13.kmac_app/latest/run.log

  UVM_FATAL @ 11782736820 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (37 [0x25] vs 34 [0x22]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 11782736820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

38.kmac_app.37142704694194100972015961843174955272070973106136412433764056494880161821403
Line 851, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/38.kmac_app/latest/run.log

  UVM_FATAL @ 45650556045 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (135 [0x87] vs 208 [0xd0]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 45650556045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 2 failures.

13.kmac_entropy_refresh.68332604485904029739184009633944021354734845414281758155447877057219204302120
Line 417, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/13.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 11294309455 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (4 [0x4] vs 128 [0x80]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 11294309455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

21.kmac_entropy_refresh.53409315860971930005394566915133444056838981262450055385029575462760852431427
Line 871, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/21.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 62263042654 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (223 [0xdf] vs 74 [0x4a]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 62263042654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 1 failures.

34.kmac_stress_all.106504572855064436563495085629997308528226727977391733481722142745492074191764
Line 299, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/34.kmac_stress_all/latest/run.log

  UVM_FATAL @ 1508427010 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (22 [0x16] vs 137 [0x89]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 1508427010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 4 failures:
- Test kmac_stress_all_with_rand_reset has 4 failures.
  - 2.kmac_stress_all_with_rand_reset.62074426721123367015810215373528535165789178727512602058627430834396405526033
    Line 332, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2904779707 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483752 [0x80000068]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 2904779707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.kmac_stress_all_with_rand_reset.45370303305338299493345202213360778155067150625944800199606302846523231863450
    Line 575, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 39693592325 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483648 [0x80000000]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 39693592325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_* reset value: * has 1 failures:
- Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.
  - 5.kmac_shadow_reg_errors_with_csr_rw.14646815947137491496302927804744696166703218357130764943862565235770368425601
    Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @  15703586 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1059140338 [0x3f2132f2] vs 1507893865 [0x59e0a269]) Regname: kmac_reg_block.prefix_8 reset value: 0x0
  UVM_INFO @  15703586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (kmac_base_vseq.sv:382) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set! has 1 failures:
- Test kmac_key_error has 1 failures.
  - 6.kmac_key_error.38056376257136774012668923495676672728416134651870447256785899158117148381839
    Line 265, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_key_error/latest/run.log
```
  UVM_ERROR @ 11199647600 ps: (kmac_base_vseq.sv:382) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
  UVM_INFO @ 11199647600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_burst_write has 1 failures.
  - 34.kmac_burst_write.27189604241545908407155822275092522240199939559196922322040414121352614202899
    Line 627, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/34.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.err_code reset value: * has 1 failures:
- Test kmac_key_error has 1 failures.
  - 48.kmac_key_error.40089753864825065049911059971202520089111083042885832038593320424149366899034
    Line 251, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/48.kmac_key_error/latest/run.log
```
  UVM_ERROR @  93980774 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 16777216 [0x1000000]) Regname: kmac_reg_block.err_code reset value: 0x0
  UVM_INFO @  93980774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```