KMAC/UNMASKED Simulation Results

Tuesday July 16 2024 23:15:02 UTC

GitHub Revision: `aad711e1bc`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 38297581588405771015102977205739484163575733999253050480227719508149669635625

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.085m	11.822ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.140s	35.147us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.210s	52.717us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	21.350s	5.778ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.640s	929.856us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.650s	303.762us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.210s	52.717us	20	20	100.00
		kmac_csr_aliasing	9.640s	929.856us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.720s	43.312us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.630s	178.107us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	46.739m	803.849ms	50	50	100.00
V2	burst_write	kmac_burst_write	15.771m	151.948ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	34.518m	197.895ms	50	50	100.00
		kmac_test_vectors_sha3_256	34.200m	733.887ms	50	50	100.00
		kmac_test_vectors_sha3_384	25.063m	147.251ms	50	50	100.00
		kmac_test_vectors_sha3_512	19.320m	550.758ms	50	50	100.00
		kmac_test_vectors_shake_128	1.560h	1.058s	50	50	100.00
		kmac_test_vectors_shake_256	1.365h	1.694s	50	50	100.00
		kmac_test_vectors_kmac	5.940s	1.046ms	50	50	100.00
		kmac_test_vectors_kmac_xof	6.020s	996.882us	50	50	100.00
V2	sideload	kmac_sideload	7.442m	43.033ms	50	50	100.00
V2	app	kmac_app	5.910m	35.333ms	47	50	94.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.404m	183.308ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.290m	6.808ms	49	50	98.00
V2	error	kmac_error	6.375m	4.842ms	50	50	100.00
V2	key_error	kmac_key_error	10.110s	6.203ms	49	50	98.00
V2	edn_timeout_error	kmac_edn_timeout_error	51.130s	38.308ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	37.650s	1.781ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.274m	15.106ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	54.320s	3.347ms	50	50	100.00
V2	stress_all	kmac_stress_all	50.774m	137.881ms	49	50	98.00
V2	intr_test	kmac_intr_test	0.840s	47.850us	50	50	100.00
V2	alert_test	kmac_alert_test	0.860s	19.454us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.120s	62.632us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.120s	62.632us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.140s	35.147us	5	5	100.00
		kmac_csr_rw	1.210s	52.717us	20	20	100.00
		kmac_csr_aliasing	9.640s	929.856us	5	5	100.00
		kmac_same_csr_outstanding	2.550s	212.502us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.140s	35.147us	5	5	100.00
		kmac_csr_rw	1.210s	52.717us	20	20	100.00
		kmac_csr_aliasing	9.640s	929.856us	5	5	100.00
		kmac_same_csr_outstanding	2.550s	212.502us	20	20	100.00
V2		TOTAL			1044	1050	99.43
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.470s	172.898us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.470s	172.898us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.470s	172.898us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.470s	172.898us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.050s	165.044us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.136m	4.797ms	5	5	100.00
		kmac_tl_intg_err	5.230s	940.347us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.230s	940.347us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	54.320s	3.347ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.085m	11.822ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.442m	43.033ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.470s	172.898us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.136m	4.797ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.136m	4.797ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.136m	4.797ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.085m	11.822ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	54.320s	3.347ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.136m	4.797ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	3.627m	11.221ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.085m	11.822ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	16.378m	57.577ms	2	10	20.00
V3		TOTAL			2	10	20.00
		TOTAL			1236	1250	98.88

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	21	84.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.33	95.89	92.30	100.00	68.60	94.11	98.84	96.58

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 8 failures:
- Test kmac_stress_all_with_rand_reset has 8 failures.
  - 0.kmac_stress_all_with_rand_reset.41490122785210625966286795812135852363349944733718781147045576390104130321417
    Line 1537, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 57576758788 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 57576758788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.84879623492831780131936083164004141163898184991858253553146512418035543459369
    Line 997, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 67953998520 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 67953998520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 4 failures:

Test kmac_entropy_refresh has 1 failures.

1.kmac_entropy_refresh.68811780082959958566362817310653317280600842273628788377295441245466631717318
Line 405, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 5828525602 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (156 [0x9c] vs 197 [0xc5]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 5828525602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 2 failures.

5.kmac_app.103397188814635700928739074715434595221357978101224490029814879179160267794734
Line 723, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_app/latest/run.log

  UVM_FATAL @ 13112684859 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (213 [0xd5] vs 166 [0xa6]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 13112684859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

45.kmac_app.8595137912280922829957903717220475800883575537025747957393705698948454581799
Line 487, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/45.kmac_app/latest/run.log

  UVM_FATAL @ 11280812504 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (187 [0xbb] vs 209 [0xd1]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 11280812504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 1 failures.

36.kmac_stress_all.41561072376202189979030280413843205162731249841771654594554161699178270846298
Line 907, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/36.kmac_stress_all/latest/run.log

  UVM_FATAL @ 4068078697 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (98 [0x62] vs 221 [0xdd]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 4068078697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_app has 1 failures.
  - 11.kmac_app.106134206084841031414751576160041948850272695721631714887614066862528183075038
    Line 949, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_app/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (kmac_base_vseq.sv:382) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set! has 1 failures:
- Test kmac_key_error has 1 failures.
  - 24.kmac_key_error.100460454361356720805855265756715869464963563679713061999049991592830803632950
    Line 259, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/24.kmac_key_error/latest/run.log
```
  UVM_ERROR @ 429772522 ps: (kmac_base_vseq.sv:382) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
  UVM_INFO @ 429772522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```