KMAC/UNMASKED Simulation Results

Wednesday July 17 2024 23:02:16 UTC

GitHub Revision: 8b2da8db5e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 31877364624131593519988921539075110140045739991215723614576185349550879231344

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke kmac_smoke 1.196m 26.128ms 50 50 100.00
V1 csr_hw_reset kmac_csr_hw_reset 1.170s 77.241us 5 5 100.00
V1 csr_rw kmac_csr_rw 1.190s 104.876us 20 20 100.00
V1 csr_bit_bash kmac_csr_bit_bash 18.610s 1.258ms 5 5 100.00
V1 csr_aliasing kmac_csr_aliasing 10.150s 1.035ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset kmac_csr_mem_rw_with_rand_reset 2.700s 79.410us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr kmac_csr_rw 1.190s 104.876us 20 20 100.00
kmac_csr_aliasing 10.150s 1.035ms 5 5 100.00
V1 mem_walk kmac_mem_walk 0.820s 54.564us 5 5 100.00
V1 mem_partial_access kmac_mem_partial_access 1.430s 59.937us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 long_msg_and_output kmac_long_msg_and_output 46.893m 132.482ms 50 50 100.00
V2 burst_write kmac_burst_write 12.919m 10.111ms 49 50 98.00
V2 test_vectors kmac_test_vectors_sha3_224 40.223m 1.655s 50 50 100.00
kmac_test_vectors_sha3_256 32.658m 97.140ms 50 50 100.00
kmac_test_vectors_sha3_384 26.007m 74.957ms 50 50 100.00
kmac_test_vectors_sha3_512 17.836m 205.527ms 50 50 100.00
kmac_test_vectors_shake_128 1.516h 1.079s 50 50 100.00
kmac_test_vectors_shake_256 1.282h 843.307ms 50 50 100.00
kmac_test_vectors_kmac 6.140s 2.998ms 50 50 100.00
kmac_test_vectors_kmac_xof 5.980s 1.032ms 50 50 100.00
V2 sideload kmac_sideload 6.691m 13.986ms 50 50 100.00
V2 app kmac_app 5.924m 13.730ms 48 50 96.00
V2 app_with_partial_data kmac_app_with_partial_data 4.145m 58.228ms 9 10 90.00
V2 entropy_refresh kmac_entropy_refresh 5.699m 15.222ms 49 50 98.00
V2 error kmac_error 6.968m 93.439ms 50 50 100.00
V2 key_error kmac_key_error 11.800s 18.352ms 50 50 100.00
V2 edn_timeout_error kmac_edn_timeout_error 46.360s 10.984ms 20 20 100.00
V2 entropy_mode_error kmac_entropy_mode_error 32.800s 553.988us 20 20 100.00
V2 entropy_ready_error kmac_entropy_ready_error 1.180m 28.870ms 10 10 100.00
V2 lc_escalation kmac_lc_escalation 22.710s 559.146us 50 50 100.00
V2 stress_all kmac_stress_all 37.944m 29.580ms 50 50 100.00
V2 intr_test kmac_intr_test 0.850s 49.651us 50 50 100.00
V2 alert_test kmac_alert_test 0.920s 35.590us 50 50 100.00
V2 tl_d_oob_addr_access kmac_tl_errors 3.680s 156.231us 20 20 100.00
V2 tl_d_illegal_access kmac_tl_errors 3.680s 156.231us 20 20 100.00
V2 tl_d_outstanding_access kmac_csr_hw_reset 1.170s 77.241us 5 5 100.00
kmac_csr_rw 1.190s 104.876us 20 20 100.00
kmac_csr_aliasing 10.150s 1.035ms 5 5 100.00
kmac_same_csr_outstanding 2.970s 517.506us 20 20 100.00
V2 tl_d_partial_access kmac_csr_hw_reset 1.170s 77.241us 5 5 100.00
kmac_csr_rw 1.190s 104.876us 20 20 100.00
kmac_csr_aliasing 10.150s 1.035ms 5 5 100.00
kmac_same_csr_outstanding 2.970s 517.506us 20 20 100.00
V2 TOTAL 1045 1050 99.52
V2S shadow_reg_update_error kmac_shadow_reg_errors 1.520s 77.054us 20 20 100.00
V2S shadow_reg_read_clear_staged_value kmac_shadow_reg_errors 1.520s 77.054us 20 20 100.00
V2S shadow_reg_storage_error kmac_shadow_reg_errors 1.520s 77.054us 20 20 100.00
V2S shadowed_reset_glitch kmac_shadow_reg_errors 1.520s 77.054us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw kmac_shadow_reg_errors_with_csr_rw 3.100s 143.082us 20 20 100.00
V2S tl_intg_err kmac_sec_cm 1.467m 49.656ms 5 5 100.00
kmac_tl_intg_err 4.640s 211.372us 20 20 100.00
V2S sec_cm_bus_integrity kmac_tl_intg_err 4.640s 211.372us 20 20 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi kmac_lc_escalation 22.710s 559.146us 50 50 100.00
V2S sec_cm_sw_key_key_masking kmac_smoke 1.196m 26.128ms 50 50 100.00
V2S sec_cm_key_sideload kmac_sideload 6.691m 13.986ms 50 50 100.00
V2S sec_cm_cfg_shadowed_config_shadow kmac_shadow_reg_errors 1.520s 77.054us 20 20 100.00
V2S sec_cm_fsm_sparse kmac_sec_cm 1.467m 49.656ms 5 5 100.00
V2S sec_cm_ctr_redun kmac_sec_cm 1.467m 49.656ms 5 5 100.00
V2S sec_cm_packer_ctr_redun kmac_sec_cm 1.467m 49.656ms 5 5 100.00
V2S sec_cm_cfg_shadowed_config_regwen kmac_smoke 1.196m 26.128ms 50 50 100.00
V2S sec_cm_fsm_global_esc kmac_lc_escalation 22.710s 559.146us 50 50 100.00
V2S sec_cm_fsm_local_esc kmac_sec_cm 1.467m 49.656ms 5 5 100.00
V2S sec_cm_absorbed_ctrl_mubi kmac_mubi 5.316m 34.472ms 10 10 100.00
V2S sec_cm_sw_cmd_ctrl_sparse kmac_smoke 1.196m 26.128ms 50 50 100.00
V2S TOTAL 75 75 100.00
V3 throughput kmac_throughput 0 0 --
V3 stress_all_with_rand_reset kmac_stress_all_with_rand_reset 17.127m 71.178ms 1 10 10.00
V3 TOTAL 1 10 10.00
TOTAL 1236 1250 98.88

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 25 25 21 84.00
V2S 5 5 5 100.00
V3 2 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
92.07 95.89 92.30 100.00 66.94 94.11 98.84 96.43

Failure Buckets

Past Results