8b2da8db5e
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | kmac_smoke | 1.196m | 26.128ms | 50 | 50 | 100.00 |
V1 | csr_hw_reset | kmac_csr_hw_reset | 1.170s | 77.241us | 5 | 5 | 100.00 |
V1 | csr_rw | kmac_csr_rw | 1.190s | 104.876us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | kmac_csr_bit_bash | 18.610s | 1.258ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | kmac_csr_aliasing | 10.150s | 1.035ms | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | kmac_csr_mem_rw_with_rand_reset | 2.700s | 79.410us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | kmac_csr_rw | 1.190s | 104.876us | 20 | 20 | 100.00 |
kmac_csr_aliasing | 10.150s | 1.035ms | 5 | 5 | 100.00 | ||
V1 | mem_walk | kmac_mem_walk | 0.820s | 54.564us | 5 | 5 | 100.00 |
V1 | mem_partial_access | kmac_mem_partial_access | 1.430s | 59.937us | 5 | 5 | 100.00 |
V1 | TOTAL | 115 | 115 | 100.00 | |||
V2 | long_msg_and_output | kmac_long_msg_and_output | 46.893m | 132.482ms | 50 | 50 | 100.00 |
V2 | burst_write | kmac_burst_write | 12.919m | 10.111ms | 49 | 50 | 98.00 |
V2 | test_vectors | kmac_test_vectors_sha3_224 | 40.223m | 1.655s | 50 | 50 | 100.00 |
kmac_test_vectors_sha3_256 | 32.658m | 97.140ms | 50 | 50 | 100.00 | ||
kmac_test_vectors_sha3_384 | 26.007m | 74.957ms | 50 | 50 | 100.00 | ||
kmac_test_vectors_sha3_512 | 17.836m | 205.527ms | 50 | 50 | 100.00 | ||
kmac_test_vectors_shake_128 | 1.516h | 1.079s | 50 | 50 | 100.00 | ||
kmac_test_vectors_shake_256 | 1.282h | 843.307ms | 50 | 50 | 100.00 | ||
kmac_test_vectors_kmac | 6.140s | 2.998ms | 50 | 50 | 100.00 | ||
kmac_test_vectors_kmac_xof | 5.980s | 1.032ms | 50 | 50 | 100.00 | ||
V2 | sideload | kmac_sideload | 6.691m | 13.986ms | 50 | 50 | 100.00 |
V2 | app | kmac_app | 5.924m | 13.730ms | 48 | 50 | 96.00 |
V2 | app_with_partial_data | kmac_app_with_partial_data | 4.145m | 58.228ms | 9 | 10 | 90.00 |
V2 | entropy_refresh | kmac_entropy_refresh | 5.699m | 15.222ms | 49 | 50 | 98.00 |
V2 | error | kmac_error | 6.968m | 93.439ms | 50 | 50 | 100.00 |
V2 | key_error | kmac_key_error | 11.800s | 18.352ms | 50 | 50 | 100.00 |
V2 | edn_timeout_error | kmac_edn_timeout_error | 46.360s | 10.984ms | 20 | 20 | 100.00 |
V2 | entropy_mode_error | kmac_entropy_mode_error | 32.800s | 553.988us | 20 | 20 | 100.00 |
V2 | entropy_ready_error | kmac_entropy_ready_error | 1.180m | 28.870ms | 10 | 10 | 100.00 |
V2 | lc_escalation | kmac_lc_escalation | 22.710s | 559.146us | 50 | 50 | 100.00 |
V2 | stress_all | kmac_stress_all | 37.944m | 29.580ms | 50 | 50 | 100.00 |
V2 | intr_test | kmac_intr_test | 0.850s | 49.651us | 50 | 50 | 100.00 |
V2 | alert_test | kmac_alert_test | 0.920s | 35.590us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | kmac_tl_errors | 3.680s | 156.231us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | kmac_tl_errors | 3.680s | 156.231us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | kmac_csr_hw_reset | 1.170s | 77.241us | 5 | 5 | 100.00 |
kmac_csr_rw | 1.190s | 104.876us | 20 | 20 | 100.00 | ||
kmac_csr_aliasing | 10.150s | 1.035ms | 5 | 5 | 100.00 | ||
kmac_same_csr_outstanding | 2.970s | 517.506us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | kmac_csr_hw_reset | 1.170s | 77.241us | 5 | 5 | 100.00 |
kmac_csr_rw | 1.190s | 104.876us | 20 | 20 | 100.00 | ||
kmac_csr_aliasing | 10.150s | 1.035ms | 5 | 5 | 100.00 | ||
kmac_same_csr_outstanding | 2.970s | 517.506us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 1045 | 1050 | 99.52 | |||
V2S | shadow_reg_update_error | kmac_shadow_reg_errors | 1.520s | 77.054us | 20 | 20 | 100.00 |
V2S | shadow_reg_read_clear_staged_value | kmac_shadow_reg_errors | 1.520s | 77.054us | 20 | 20 | 100.00 |
V2S | shadow_reg_storage_error | kmac_shadow_reg_errors | 1.520s | 77.054us | 20 | 20 | 100.00 |
V2S | shadowed_reset_glitch | kmac_shadow_reg_errors | 1.520s | 77.054us | 20 | 20 | 100.00 |
V2S | shadow_reg_update_error_with_csr_rw | kmac_shadow_reg_errors_with_csr_rw | 3.100s | 143.082us | 20 | 20 | 100.00 |
V2S | tl_intg_err | kmac_sec_cm | 1.467m | 49.656ms | 5 | 5 | 100.00 |
kmac_tl_intg_err | 4.640s | 211.372us | 20 | 20 | 100.00 | ||
V2S | sec_cm_bus_integrity | kmac_tl_intg_err | 4.640s | 211.372us | 20 | 20 | 100.00 |
V2S | sec_cm_lc_escalate_en_intersig_mubi | kmac_lc_escalation | 22.710s | 559.146us | 50 | 50 | 100.00 |
V2S | sec_cm_sw_key_key_masking | kmac_smoke | 1.196m | 26.128ms | 50 | 50 | 100.00 |
V2S | sec_cm_key_sideload | kmac_sideload | 6.691m | 13.986ms | 50 | 50 | 100.00 |
V2S | sec_cm_cfg_shadowed_config_shadow | kmac_shadow_reg_errors | 1.520s | 77.054us | 20 | 20 | 100.00 |
V2S | sec_cm_fsm_sparse | kmac_sec_cm | 1.467m | 49.656ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctr_redun | kmac_sec_cm | 1.467m | 49.656ms | 5 | 5 | 100.00 |
V2S | sec_cm_packer_ctr_redun | kmac_sec_cm | 1.467m | 49.656ms | 5 | 5 | 100.00 |
V2S | sec_cm_cfg_shadowed_config_regwen | kmac_smoke | 1.196m | 26.128ms | 50 | 50 | 100.00 |
V2S | sec_cm_fsm_global_esc | kmac_lc_escalation | 22.710s | 559.146us | 50 | 50 | 100.00 |
V2S | sec_cm_fsm_local_esc | kmac_sec_cm | 1.467m | 49.656ms | 5 | 5 | 100.00 |
V2S | sec_cm_absorbed_ctrl_mubi | kmac_mubi | 5.316m | 34.472ms | 10 | 10 | 100.00 |
V2S | sec_cm_sw_cmd_ctrl_sparse | kmac_smoke | 1.196m | 26.128ms | 50 | 50 | 100.00 |
V2S | TOTAL | 75 | 75 | 100.00 | |||
V3 | throughput | kmac_throughput | 0 | 0 | -- | ||
V3 | stress_all_with_rand_reset | kmac_stress_all_with_rand_reset | 17.127m | 71.178ms | 1 | 10 | 10.00 |
V3 | TOTAL | 1 | 10 | 10.00 | |||
TOTAL | 1236 | 1250 | 98.88 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 8 | 8 | 8 | 100.00 |
V2 | 25 | 25 | 21 | 84.00 |
V2S | 5 | 5 | 5 | 100.00 |
V3 | 2 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
92.07 | 95.89 | 92.30 | 100.00 | 66.94 | 94.11 | 98.84 | 96.43 |
UVM_ERROR (cip_base_vseq.sv:839) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
has 8 failures:
0.kmac_stress_all_with_rand_reset.8336049366319397186614344517306889439877125098585195731237000275047366095589
Line 520, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 70821077979 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 70821077979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.kmac_stress_all_with_rand_reset.69415333813964574714323877208365820688969988283852130195961840094157303781917
Line 1440, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 153377035134 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 153377035134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*]
has 3 failures:
Test kmac_app_with_partial_data has 1 failures.
9.kmac_app_with_partial_data.40355516134069819723629968357548308996149882091944079253841643207708377911659
Line 341, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_app_with_partial_data/latest/run.log
UVM_FATAL @ 2936216573 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (80 [0x50] vs 111 [0x6f]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 2936216573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_app has 2 failures.
21.kmac_app.24559129466217183710220404474338787860267477335182206611344892085040384109315
Line 401, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/21.kmac_app/latest/run.log
UVM_FATAL @ 2704425574 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (97 [0x61] vs 72 [0x48]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 2704425574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
24.kmac_app.89056429508847999725979547978303781404793426476995322579000403870552256099563
Line 953, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/24.kmac_app/latest/run.log
UVM_FATAL @ 20814800176 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (174 [0xae] vs 12 [0xc]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 20814800176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
has 2 failures:
Test kmac_burst_write has 1 failures.
0.kmac_burst_write.114714214125040481169194971251743397693036057268399384552560724464404295704904
Line 1142, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_burst_write/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_entropy_refresh has 1 failures.
6.kmac_entropy_refresh.57489994143460722039920504798920397463179284230650364784718184206260869629672
Line 844, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_entropy_refresh/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code
has 1 failures:
5.kmac_stress_all_with_rand_reset.83320215978713296665322409806079512423531500009254289867078953125585668370672
Line 413, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 684950771 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483744 [0x80000060]) reg name: kmac_reg_block.err_code
UVM_INFO @ 684950771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---