KMAC/UNMASKED Simulation Results

Thursday July 18 2024 23:02:12 UTC

GitHub Revision: `974aaab627`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 46057207235241274571178436692064798722168129065126426307050395083305588858879

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.058m	6.458ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.070s	175.628us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.230s	29.805us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	19.470s	2.493ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.020s	1.855ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.740s	290.939us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.230s	29.805us	20	20	100.00
		kmac_csr_aliasing	10.020s	1.855ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.760s	20.633us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.450s	37.526us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	49.721m	134.043ms	50	50	100.00
V2	burst_write	kmac_burst_write	14.599m	136.001ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	34.723m	468.677ms	50	50	100.00
		kmac_test_vectors_sha3_256	32.448m	193.579ms	50	50	100.00
		kmac_test_vectors_sha3_384	27.783m	703.967ms	50	50	100.00
		kmac_test_vectors_sha3_512	18.259m	96.663ms	50	50	100.00
		kmac_test_vectors_shake_128	1.666h	2.567s	50	50	100.00
		kmac_test_vectors_shake_256	1.286h	1.093s	50	50	100.00
		kmac_test_vectors_kmac	5.340s	581.492us	50	50	100.00
		kmac_test_vectors_kmac_xof	6.250s	3.423ms	50	50	100.00
V2	sideload	kmac_sideload	7.427m	43.737ms	50	50	100.00
V2	app	kmac_app	5.319m	200.000ms	48	50	96.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.324m	25.306ms	9	10	90.00
V2	entropy_refresh	kmac_entropy_refresh	5.054m	6.127ms	49	50	98.00
V2	error	kmac_error	7.474m	64.933ms	50	50	100.00
V2	key_error	kmac_key_error	12.160s	12.776ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	46.660s	16.331ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	38.100s	2.039ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.157m	29.835ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	27.800s	2.080ms	50	50	100.00
V2	stress_all	kmac_stress_all	28.296m	22.111ms	47	50	94.00
V2	intr_test	kmac_intr_test	0.910s	13.993us	50	50	100.00
V2	alert_test	kmac_alert_test	0.940s	159.958us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.420s	145.022us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.420s	145.022us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.070s	175.628us	5	5	100.00
		kmac_csr_rw	1.230s	29.805us	20	20	100.00
		kmac_csr_aliasing	10.020s	1.855ms	5	5	100.00
		kmac_same_csr_outstanding	2.900s	509.592us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.070s	175.628us	5	5	100.00
		kmac_csr_rw	1.230s	29.805us	20	20	100.00
		kmac_csr_aliasing	10.020s	1.855ms	5	5	100.00
		kmac_same_csr_outstanding	2.900s	509.592us	20	20	100.00
V2		TOTAL			1043	1050	99.33
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.350s	95.349us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.350s	95.349us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.350s	95.349us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.350s	95.349us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.100s	495.848us	18	20	90.00
V2S	tl_intg_err	kmac_sec_cm	1.284m	24.359ms	5	5	100.00
		kmac_tl_intg_err	5.420s	364.871us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.420s	364.871us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	27.800s	2.080ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.058m	6.458ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.427m	43.737ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.350s	95.349us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.284m	24.359ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.284m	24.359ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.284m	24.359ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.058m	6.458ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	27.800s	2.080ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.284m	24.359ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.744m	19.083ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.058m	6.458ms	50	50	100.00
V2S		TOTAL			73	75	97.33
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	22.704m	31.253ms	3	10	30.00
V3		TOTAL			3	10	30.00
		TOTAL			1234	1250	98.72

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	21	84.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.17	95.89	92.30	100.00	67.77	94.11	98.84	96.29

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:839) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:
- Test kmac_stress_all_with_rand_reset has 7 failures.
  - 0.kmac_stress_all_with_rand_reset.89341017962657037165410443070707157902060372244172962280847671718957852625746
    Line 303, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1210987894 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1210987894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.93479013984395540920213420926875980478683016638129675716891769437125736086070
    Line 422, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 15047921503 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 15047921503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 6 failures:

Test kmac_stress_all has 3 failures.

4.kmac_stress_all.75721183593237677723100613632172889886325060724078064699430067854556927159535
Line 565, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_stress_all/latest/run.log

  UVM_FATAL @ 2318018341 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (127 [0x7f] vs 70 [0x46]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 2318018341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

43.kmac_stress_all.49253560787040888586606420814333204804939400502278454223692048576318191938717
Line 2105, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/43.kmac_stress_all/latest/run.log

  UVM_FATAL @ 416087366531 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (160 [0xa0] vs 73 [0x49]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 416087366531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test kmac_app_with_partial_data has 1 failures.

5.kmac_app_with_partial_data.106811159613919180882269848695191535384379310734475869000927524357399272755462
Line 473, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_app_with_partial_data/latest/run.log

  UVM_FATAL @ 4902292094 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (8 [0x8] vs 96 [0x60]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 4902292094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 1 failures.

20.kmac_app.5934028807857441639435964365392038848592078526954014106987102747275119449175
Line 489, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/20.kmac_app/latest/run.log

  UVM_FATAL @ 1177121614 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (152 [0x98] vs 197 [0xc5]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 1177121614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 1 failures.

35.kmac_entropy_refresh.34203285598898867028351202463784233165966431139629731998758146682838529740467
Line 405, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/35.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 10775642832 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (45 [0x2d] vs 167 [0xa7]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 10775642832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_* reset value: * has 1 failures:
- Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.
  - 2.kmac_shadow_reg_errors_with_csr_rw.98375604977167947706838270809843955390461824701211833725407939677578549280787
    Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @  28023058 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (271165017 [0x1029a659] vs 1702826844 [0x657f135c]) Regname: kmac_reg_block.prefix_5 reset value: 0x0
  UVM_INFO @  28023058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_app has 1 failures.
  - 5.kmac_app.30066315945323970266708658604234897812068449184559347998589715777828289209597
    Line 1036, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_app/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_*.prefix_* reset value: * has 1 failures:
- Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.
  - 9.kmac_shadow_reg_errors_with_csr_rw.8433239364266304752330532668262309840829194014354537171804903886705066779097
    Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @   1947665 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (3318800330 [0xc5d0dfca] vs 0 [0x0]) Regname: kmac_reg_block.prefix_0.prefix_0 reset value: 0x0
  UVM_INFO @   1947665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```