KMAC/UNMASKED Simulation Results

Saturday August 24 2024 20:58:08 UTC

GitHub Revision: e733a8ef8a

Branch: os_regression_2024_08_24

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 36240513409906943553650221581975102764006655953510936167454320581301243659163

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.615m	8.511ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.790s	220.180us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.980s	36.226us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	30.940s	2.611ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.700s	1.161ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.830s	39.479us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.980s	36.226us	20	20	100.00
		kmac_csr_aliasing	7.700s	1.161ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	1.190s	14.839us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.830s	424.402us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	1.730h	496.877ms	50	50	100.00
V2	burst_write	kmac_burst_write	25.831m	145.433ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	53.679m	361.106ms	5	5	100.00
		kmac_test_vectors_sha3_256	53.545m	319.803ms	5	5	100.00
		kmac_test_vectors_sha3_384	36.127m	164.347ms	5	5	100.00
		kmac_test_vectors_sha3_512	16.820m	125.693ms	5	5	100.00
		kmac_test_vectors_shake_128	1.173h	441.233ms	5	5	100.00
		kmac_test_vectors_shake_256	51.697m	300.661ms	5	5	100.00
		kmac_test_vectors_kmac	3.410s	49.348us	5	5	100.00
		kmac_test_vectors_kmac_xof	4.030s	225.932us	5	5	100.00
V2	sideload	kmac_sideload	10.806m	84.129ms	50	50	100.00
V2	app	kmac_app	8.945m	36.419ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.588m	12.668ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	10.250m	182.870ms	49	50	98.00
V2	error	kmac_error	10.784m	21.786ms	50	50	100.00
V2	key_error	kmac_key_error	21.920s	8.407ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	1.066m	4.419ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	57.620s	7.799ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.795m	59.892ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	56.890s	936.102us	50	50	100.00
V2	stress_all	kmac_stress_all	1.180h	107.406ms	50	50	100.00
V2	intr_test	kmac_intr_test	1.280s	23.858us	50	50	100.00
V2	alert_test	kmac_alert_test	1.330s	104.672us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	6.030s	603.708us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	6.030s	603.708us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.790s	220.180us	5	5	100.00
		kmac_csr_rw	1.980s	36.226us	20	20	100.00
		kmac_csr_aliasing	7.700s	1.161ms	5	5	100.00
		kmac_same_csr_outstanding	3.990s	114.986us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.790s	220.180us	5	5	100.00
		kmac_csr_rw	1.980s	36.226us	20	20	100.00
		kmac_csr_aliasing	7.700s	1.161ms	5	5	100.00
		kmac_same_csr_outstanding	3.990s	114.986us	20	20	100.00
V2		TOTAL			688	690	99.71
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.330s	117.428us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.330s	117.428us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.330s	117.428us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.330s	117.428us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.020s	795.066us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.034m	12.569ms	5	5	100.00
		kmac_tl_intg_err	7.890s	263.529us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	7.890s	263.529us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	56.890s	936.102us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.615m	8.511ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	10.806m	84.129ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.330s	117.428us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.034m	12.569ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.034m	12.569ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.034m	12.569ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.615m	8.511ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	56.890s	936.102us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.034m	12.569ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.317m	4.451ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.615m	8.511ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	4.059m	2.223ms	1	10	10.00
V3		TOTAL			1	10	10.00
		TOTAL			879	890	98.76

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	23	92.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.24	95.89	92.27	100.00	68.60	94.11	98.84	96.01

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:867) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:

  • Test kmac_stress_all_with_rand_reset has 7 failures.

    • 1.kmac_stress_all_with_rand_reset.29315939859223557674431940370013379498671869388762413982129187005609054770548
      Line 71, in log /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1547746222 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1547746222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.kmac_stress_all_with_rand_reset.84785462760999992145677915006581331852900446692674466196145809920304324356158
      Line 85, in log /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1274085661 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1274085661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 5 more failures.

• UVM_ERROR (kmac_scoreboard.sv:1188) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 2 failures:

  • Test kmac_stress_all_with_rand_reset has 2 failures.

    • 0.kmac_stress_all_with_rand_reset.4938049071004101394840551149711882013597391721561536951851196939963940246500
      Line 99, in log /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 633914480 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483680 [0x80000020]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 633914480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 6.kmac_stress_all_with_rand_reset.73302943596285790315190306690374049628379302411772598322787741856336145556336
      Line 182, in log /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/6.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1953765853 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483768 [0x80000078]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 1953765853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (kmac_scoreboard.sv:1638) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 2 failures:

  • Test kmac_app has 1 failures.

    • 26.kmac_app.98664183347662992273403201461230049880859389423891167652774922146819524869177
      Line 98, in log /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/26.kmac_app/latest/run.log

        UVM_FATAL @ 367121263 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (134 [0x86] vs 33 [0x21]) Mismatch between unmasked_digest[0] and dpi_digest[0]
        UVM_INFO @ 367121263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test kmac_entropy_refresh has 1 failures.

    • 37.kmac_entropy_refresh.51402538641889978406742522382459901071353855343925995222852343158394116326709
      Line 258, in log /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/37.kmac_entropy_refresh/latest/run.log

        UVM_FATAL @ 12760776871 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (193 [0xc1] vs 175 [0xaf]) Mismatch between unmasked_digest[0] and dpi_digest[0]
        UVM_INFO @ 12760776871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.08.24_20.05.37
• 2024.08.22_14.07.12
• 2024.08.20_07.51.06
• 2024.08.19_08.04.55
• 2024.08.18_08.33.41
• 2024.08.17_07.11.32
• 2024.08.16_08.33.07