KMAC/UNMASKED Simulation Results

Monday August 26 2024 23:33:20 UTC

GitHub Revision: 4674f625b3

Branch: os_regression_2024_08_26

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 27137705585251537962012108482438895412147493342955425380690984800523869492310

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.578m	16.495ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.710s	107.219us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.770s	128.161us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	28.000s	2.539ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.800s	544.679us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.620s	263.517us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.770s	128.161us	20	20	100.00
		kmac_csr_aliasing	10.800s	544.679us	5	5	100.00
V1	mem_walk	kmac_mem_walk	1.130s	11.674us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.170s	71.523us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	1.301h	278.162ms	50	50	100.00
V2	burst_write	kmac_burst_write	20.276m	152.455ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	42.019m	392.243ms	5	5	100.00
		kmac_test_vectors_sha3_256	40.841m	118.690ms	5	5	100.00
		kmac_test_vectors_sha3_384	31.305m	455.467ms	5	5	100.00
		kmac_test_vectors_sha3_512	22.570s	11.857ms	5	5	100.00
		kmac_test_vectors_shake_128	33.187m	335.919ms	5	5	100.00
		kmac_test_vectors_shake_256	32.266m	58.056ms	5	5	100.00
		kmac_test_vectors_kmac	3.400s	89.670us	5	5	100.00
		kmac_test_vectors_kmac_xof	3.830s	105.870us	5	5	100.00
V2	sideload	kmac_sideload	8.038m	110.283ms	50	50	100.00
V2	app	kmac_app	5.826m	66.928ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.690m	64.538ms	9	10	90.00
V2	entropy_refresh	kmac_entropy_refresh	6.610m	321.334ms	50	50	100.00
V2	error	kmac_error	7.861m	131.934ms	49	50	98.00
V2	key_error	kmac_key_error	16.890s	5.717ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	51.510s	11.763ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	57.830s	8.588ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	58.430s	43.140ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	28.450s	362.259us	50	50	100.00
V2	stress_all	kmac_stress_all	36.498m	88.646ms	50	50	100.00
V2	intr_test	kmac_intr_test	1.280s	150.006us	50	50	100.00
V2	alert_test	kmac_alert_test	1.300s	16.714us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	5.000s	609.543us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	5.000s	609.543us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.710s	107.219us	5	5	100.00
		kmac_csr_rw	1.770s	128.161us	20	20	100.00
		kmac_csr_aliasing	10.800s	544.679us	5	5	100.00
		kmac_same_csr_outstanding	3.540s	179.070us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.710s	107.219us	5	5	100.00
		kmac_csr_rw	1.770s	128.161us	20	20	100.00
		kmac_csr_aliasing	10.800s	544.679us	5	5	100.00
		kmac_same_csr_outstanding	3.540s	179.070us	20	20	100.00
V2		TOTAL			687	690	99.57
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.030s	66.075us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.030s	66.075us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.030s	66.075us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.030s	66.075us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.850s	104.143us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.355m	25.991ms	5	5	100.00
		kmac_tl_intg_err	7.750s	510.648us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	7.750s	510.648us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	28.450s	362.259us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.578m	16.495ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	8.038m	110.283ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.030s	66.075us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.355m	25.991ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.355m	25.991ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.355m	25.991ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.578m	16.495ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	28.450s	362.259us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.355m	25.991ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.594m	43.924ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.578m	16.495ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	6.003m	19.179ms	2	10	20.00
V3		TOTAL			2	10	20.00
		TOTAL			879	890	98.76

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	22	88.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.13	95.89	92.30	100.00	67.77	94.11	98.84	96.01

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:867) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:

  • Test kmac_stress_all_with_rand_reset has 7 failures.

    • 1.kmac_stress_all_with_rand_reset.60285981360191382920955548812796810516712812036541647516304278410524495317101
      Line 118, in log /workspaces/repo/scratch/os_regression_2024_08_26/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1899160563 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1899160563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.kmac_stress_all_with_rand_reset.30790143195604504352201015236845752498536568731448593963383846537710576953592
      Line 135, in log /workspaces/repo/scratch/os_regression_2024_08_26/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1961269808 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1961269808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 5 more failures.

• UVM_FATAL (kmac_scoreboard.sv:1638) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 2 failures:

  • Test kmac_app_with_partial_data has 1 failures.

    • 9.kmac_app_with_partial_data.111532125797587747941163534136046636534720873120380470931335734532414751779316
      Line 142, in log /workspaces/repo/scratch/os_regression_2024_08_26/kmac_unmasked-sim-vcs/9.kmac_app_with_partial_data/latest/run.log

        UVM_FATAL @ 8208888991 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (226 [0xe2] vs 94 [0x5e]) Mismatch between unmasked_digest[0] and dpi_digest[0]
        UVM_INFO @ 8208888991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test kmac_app has 1 failures.

    • 27.kmac_app.17118300940987305074391529139381389168381392839849457321358206970416913636727
      Line 132, in log /workspaces/repo/scratch/os_regression_2024_08_26/kmac_unmasked-sim-vcs/27.kmac_app/latest/run.log

        UVM_FATAL @ 5704240888 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (252 [0xfc] vs 104 [0x68]) Mismatch between unmasked_digest[0] and dpi_digest[0]
        UVM_INFO @ 5704240888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (kmac_scoreboard.sv:1188) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 3.kmac_stress_all_with_rand_reset.109128120352198273123631076261409945615863773013265574615636334277648105350726
      Line 87, in log /workspaces/repo/scratch/os_regression_2024_08_26/kmac_unmasked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 392374701 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483680 [0x80000020]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 392374701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test kmac_error has 1 failures.

    • 4.kmac_error.88349783686890733800132012741361871404041694157397386755748692807161764031544
      Line 935, in log /workspaces/repo/scratch/os_regression_2024_08_26/kmac_unmasked-sim-vcs/4.kmac_error/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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