KMAC/UNMASKED Simulation Results

Wednesday August 28 2024 16:26:26 UTC

GitHub Revision: `a861deb3de`

Branch: os_regression_2024_08_28

Simulator: VCS

Build randomization enabled with --build-seed 1071354200461384473511155521960728188378582408849032283874664554749864050652

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.634m	16.456ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.390s	62.607us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.550s	34.538us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	20.010s	3.000ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.610s	456.290us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.580s	79.723us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.550s	34.538us	20	20	100.00
		kmac_csr_aliasing	9.610s	456.290us	5	5	100.00
V1	mem_walk	kmac_mem_walk	1.040s	17.086us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.650s	22.568us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	1.351h	710.308ms	50	50	100.00
V2	burst_write	kmac_burst_write	21.090m	143.536ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	43.703m	60.819ms	5	5	100.00
		kmac_test_vectors_sha3_256	45.312m	354.380ms	5	5	100.00
		kmac_test_vectors_sha3_384	27.494m	60.190ms	5	5	100.00
		kmac_test_vectors_sha3_512	20.970m	48.881ms	5	5	100.00
		kmac_test_vectors_shake_128	47.529m	427.950ms	5	5	100.00
		kmac_test_vectors_shake_256	6.299m	19.610ms	5	5	100.00
		kmac_test_vectors_kmac	3.600s	302.629us	5	5	100.00
		kmac_test_vectors_kmac_xof	3.170s	35.650us	5	5	100.00
V2	sideload	kmac_sideload	10.082m	127.784ms	50	50	100.00
V2	app	kmac_app	7.066m	14.480ms	48	50	96.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.753m	67.557ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.431m	57.478ms	50	50	100.00
V2	error	kmac_error	8.581m	70.289ms	50	50	100.00
V2	key_error	kmac_key_error	20.450s	7.029ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	56.730s	3.277ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	50.790s	4.096ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.708m	34.023ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	1.211m	3.428ms	50	50	100.00
V2	stress_all	kmac_stress_all	56.247m	231.511ms	50	50	100.00
V2	intr_test	kmac_intr_test	1.180s	22.818us	50	50	100.00
V2	alert_test	kmac_alert_test	1.330s	24.254us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.160s	235.028us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.160s	235.028us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.390s	62.607us	5	5	100.00
		kmac_csr_rw	1.550s	34.538us	20	20	100.00
		kmac_csr_aliasing	9.610s	456.290us	5	5	100.00
		kmac_same_csr_outstanding	2.710s	1.466ms	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.390s	62.607us	5	5	100.00
		kmac_csr_rw	1.550s	34.538us	20	20	100.00
		kmac_csr_aliasing	9.610s	456.290us	5	5	100.00
		kmac_same_csr_outstanding	2.710s	1.466ms	20	20	100.00
V2		TOTAL			688	690	99.71
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.690s	240.353us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.690s	240.353us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.690s	240.353us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.690s	240.353us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.510s	554.907us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.171m	4.926ms	5	5	100.00
		kmac_tl_intg_err	5.320s	960.233us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.320s	960.233us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.211m	3.428ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.634m	16.456ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	10.082m	127.784ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.690s	240.353us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.171m	4.926ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.171m	4.926ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.171m	4.926ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.634m	16.456ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.211m	3.428ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.171m	4.926ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.382m	27.189ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.634m	16.456ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	3.831m	52.490ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			878	890	98.65

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	24	96.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
91.79	95.77	90.51	100.00	67.77	93.67	98.84	96.01

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 5 failures:
- Test kmac_stress_all_with_rand_reset has 5 failures.
  - 0.kmac_stress_all_with_rand_reset.26382265385320982282203239354953225531658355540709875823072151260937271320027
    Line 103, in log /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 841391042 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 841391042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.kmac_stress_all_with_rand_reset.68759616130427258449383163735943736443621827908289715096373519339304594080171
    Line 116, in log /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 283979038 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 283979038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_ERROR (kmac_scoreboard.sv:1188) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 5 failures:
- Test kmac_stress_all_with_rand_reset has 5 failures.
  - 1.kmac_stress_all_with_rand_reset.73965472144361478745826302073502921005183532677669109955699542292498290498864
    Line 120, in log /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1855543803 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483680 [0x80000020]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 1855543803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.kmac_stress_all_with_rand_reset.32986303506770611524449934606833568970476596546439330740889946282348628552335
    Line 683, in log /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 52489542991 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483712 [0x80000040]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 52489542991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

UVM_FATAL (kmac_scoreboard.sv:1638) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*]

has 2 failures:

Test kmac_app has 2 failures.

4.kmac_app.20801733607484173402451029825029692912567074655339629275510585350922184053816
Line 122, in log /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/4.kmac_app/latest/run.log

  UVM_FATAL @ 1316587245 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (15 [0xf] vs 119 [0x77]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 1316587245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

17.kmac_app.84742008521268080152930028701932372154808176370448520800131896126432588781336
Line 270, in log /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/17.kmac_app/latest/run.log

  UVM_FATAL @ 2716658847 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (53 [0x35] vs 43 [0x2b]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 2716658847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---