KMAC/UNMASKED Simulation Results

Sunday September 01 2024 02:56:32 UTC

GitHub Revision: `ed1c41cd0f`

Branch: os_regression_2024_08_31

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 79046303479535931055412478968949166876277637335647713094117953182855865639399

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.667m	7.298ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.760s	30.659us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.970s	340.591us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	29.710s	4.639ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	16.950s	5.416ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.900s	106.899us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.970s	340.591us	20	20	100.00
		kmac_csr_aliasing	16.950s	5.416ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	1.180s	16.282us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.280s	133.385us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	1.665h	553.450ms	50	50	100.00
V2	burst_write	kmac_burst_write	19.479m	100.131ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	47.015m	138.781ms	5	5	100.00
		kmac_test_vectors_sha3_256	41.706m	193.480ms	5	5	100.00
		kmac_test_vectors_sha3_384	31.035m	277.071ms	5	5	100.00
		kmac_test_vectors_sha3_512	23.172m	50.554ms	5	5	100.00
		kmac_test_vectors_shake_128	50.222m	294.485ms	5	5	100.00
		kmac_test_vectors_shake_256	30.286m	34.149ms	5	5	100.00
		kmac_test_vectors_kmac	4.180s	200.526us	5	5	100.00
		kmac_test_vectors_kmac_xof	4.440s	1.078ms	5	5	100.00
V2	sideload	kmac_sideload	11.141m	96.079ms	50	50	100.00
V2	app	kmac_app	7.159m	94.592ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.591m	16.030ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	8.614m	76.664ms	50	50	100.00
V2	error	kmac_error	7.860m	34.132ms	48	50	96.00
V2	key_error	kmac_key_error	25.200s	15.762ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	58.720s	18.391ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	56.840s	3.139ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.625m	39.961ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	39.250s	860.065us	50	50	100.00
V2	stress_all	kmac_stress_all	1.130h	144.112ms	50	50	100.00
V2	intr_test	kmac_intr_test	1.260s	17.722us	50	50	100.00
V2	alert_test	kmac_alert_test	1.330s	174.406us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.840s	60.319us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.840s	60.319us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.760s	30.659us	5	5	100.00
		kmac_csr_rw	1.970s	340.591us	20	20	100.00
		kmac_csr_aliasing	16.950s	5.416ms	5	5	100.00
		kmac_same_csr_outstanding	4.010s	225.216us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.760s	30.659us	5	5	100.00
		kmac_csr_rw	1.970s	340.591us	20	20	100.00
		kmac_csr_aliasing	16.950s	5.416ms	5	5	100.00
		kmac_same_csr_outstanding	4.010s	225.216us	20	20	100.00
V2		TOTAL			688	690	99.71
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.550s	790.661us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.550s	790.661us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.550s	790.661us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.550s	790.661us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	4.280s	373.735us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.641m	7.892ms	5	5	100.00
		kmac_tl_intg_err	7.460s	831.220us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	7.460s	831.220us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	39.250s	860.065us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.667m	7.298ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	11.141m	96.079ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.550s	790.661us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.641m	7.892ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.641m	7.892ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.641m	7.892ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.667m	7.298ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	39.250s	860.065us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.641m	7.892ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	7.154m	11.508ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.667m	7.298ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	2.804m	2.789ms	1	10	10.00
V3		TOTAL			1	10	10.00
		TOTAL			879	890	98.76

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	24	96.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.37	95.89	92.30	100.00	69.42	94.11	98.84	96.01

Failure Buckets

UVM_ERROR (kmac_scoreboard.sv:1196) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 7 failures:
- Test kmac_stress_all_with_rand_reset has 7 failures.
  - 0.kmac_stress_all_with_rand_reset.112416075403840240445022276760538952585668283801709302167511880014618798149032
    Line 150, in log /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10079951793 ps: (kmac_scoreboard.sv:1196) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483648 [0x80000000]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 10079951793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.kmac_stress_all_with_rand_reset.33902417152380417356556429591747864462205141858045902578115825548177489943541
    Line 280, in log /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2788766784 ps: (kmac_scoreboard.sv:1196) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483688 [0x80000028]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 2788766784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_ERROR (cip_base_vseq.sv:867) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test kmac_stress_all_with_rand_reset has 2 failures.
  - 1.kmac_stress_all_with_rand_reset.71381854403151946068082484785791838568181101588917369745046147184743431508633
    Line 130, in log /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1967867544 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1967867544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.kmac_stress_all_with_rand_reset.41546107068484835309581290886018140657146970601587818635234412532123814703922
    Line 210, in log /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/7.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2890164860 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2890164860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test kmac_error has 2 failures.
  - 25.kmac_error.39783582785718766828482564669035344587671721419549076770683741495552330013073
    Line 822, in log /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/25.kmac_error/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 44.kmac_error.30067795769409626320542235365968787344431477602892758752735732160891244592424
    Line 969, in log /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/44.kmac_error/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

KMAC/UNMASKED Simulation Results

Sunday September 01 2024 02:56:32 UTC

GitHub Revision: ed1c41cd0f

Branch: os_regression_2024_08_31

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 79046303479535931055412478968949166876277637335647713094117953182855865639399

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `ed1c41cd0f`