372a6306e0| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | kmac_smoke | 1.487m | 8.161ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | kmac_csr_hw_reset | 1.730s | 84.742us | 5 | 5 | 100.00 |
| V1 | csr_rw | kmac_csr_rw | 1.710s | 53.713us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | kmac_csr_bit_bash | 21.560s | 1.484ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | kmac_csr_aliasing | 13.650s | 1.527ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | kmac_csr_mem_rw_with_rand_reset | 3.710s | 142.453us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | kmac_csr_rw | 1.710s | 53.713us | 20 | 20 | 100.00 |
| kmac_csr_aliasing | 13.650s | 1.527ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | kmac_mem_walk | 1.190s | 22.933us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | kmac_mem_partial_access | 2.180s | 159.073us | 5 | 5 | 100.00 |
| V1 | TOTAL | 115 | 115 | 100.00 | |||
| V2 | long_msg_and_output | kmac_long_msg_and_output | 1.294h | 462.549ms | 50 | 50 | 100.00 |
| V2 | burst_write | kmac_burst_write | 21.138m | 34.856ms | 50 | 50 | 100.00 |
| V2 | test_vectors | kmac_test_vectors_sha3_224 | 58.010s | 9.363ms | 5 | 5 | 100.00 |
| kmac_test_vectors_sha3_256 | 36.934m | 76.523ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_sha3_384 | 26.388m | 47.233ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_sha3_512 | 18.431m | 515.482ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_shake_128 | 33.223m | 256.418ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_shake_256 | 39.554m | 314.253ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_kmac | 3.430s | 34.918us | 5 | 5 | 100.00 | ||
| kmac_test_vectors_kmac_xof | 3.080s | 111.287us | 5 | 5 | 100.00 | ||
| V2 | sideload | kmac_sideload | 8.027m | 74.146ms | 50 | 50 | 100.00 |
| V2 | app | kmac_app | 6.664m | 5.125ms | 50 | 50 | 100.00 |
| V2 | app_with_partial_data | kmac_app_with_partial_data | 6.611m | 163.914ms | 10 | 10 | 100.00 |
| V2 | entropy_refresh | kmac_entropy_refresh | 7.686m | 195.621ms | 50 | 50 | 100.00 |
| V2 | error | kmac_error | 8.323m | 20.821ms | 50 | 50 | 100.00 |
| V2 | key_error | kmac_key_error | 15.930s | 6.934ms | 49 | 50 | 98.00 |
| V2 | edn_timeout_error | kmac_edn_timeout_error | 39.400s | 4.757ms | 20 | 20 | 100.00 |
| V2 | entropy_mode_error | kmac_entropy_mode_error | 49.370s | 16.841ms | 20 | 20 | 100.00 |
| V2 | entropy_ready_error | kmac_entropy_ready_error | 1.381m | 24.858ms | 10 | 10 | 100.00 |
| V2 | lc_escalation | kmac_lc_escalation | 1.205m | 1.169ms | 50 | 50 | 100.00 |
| V2 | stress_all | kmac_stress_all | 48.912m | 381.071ms | 50 | 50 | 100.00 |
| V2 | intr_test | kmac_intr_test | 1.240s | 15.885us | 50 | 50 | 100.00 |
| V2 | alert_test | kmac_alert_test | 1.360s | 199.272us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | kmac_tl_errors | 5.550s | 332.570us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | kmac_tl_errors | 5.550s | 332.570us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | kmac_csr_hw_reset | 1.730s | 84.742us | 5 | 5 | 100.00 |
| kmac_csr_rw | 1.710s | 53.713us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 13.650s | 1.527ms | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 3.740s | 99.185us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | kmac_csr_hw_reset | 1.730s | 84.742us | 5 | 5 | 100.00 |
| kmac_csr_rw | 1.710s | 53.713us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 13.650s | 1.527ms | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 3.740s | 99.185us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 689 | 690 | 99.86 | |||
| V2S | shadow_reg_update_error | kmac_shadow_reg_errors | 1.960s | 53.933us | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | kmac_shadow_reg_errors | 1.960s | 53.933us | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | kmac_shadow_reg_errors | 1.960s | 53.933us | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | kmac_shadow_reg_errors | 1.960s | 53.933us | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | kmac_shadow_reg_errors_with_csr_rw | 4.380s | 409.727us | 20 | 20 | 100.00 |
| V2S | tl_intg_err | kmac_sec_cm | 1.756m | 58.422ms | 5 | 5 | 100.00 |
| kmac_tl_intg_err | 6.060s | 967.858us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | kmac_tl_intg_err | 6.060s | 967.858us | 20 | 20 | 100.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | kmac_lc_escalation | 1.205m | 1.169ms | 50 | 50 | 100.00 |
| V2S | sec_cm_sw_key_key_masking | kmac_smoke | 1.487m | 8.161ms | 50 | 50 | 100.00 |
| V2S | sec_cm_key_sideload | kmac_sideload | 8.027m | 74.146ms | 50 | 50 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_shadow | kmac_shadow_reg_errors | 1.960s | 53.933us | 20 | 20 | 100.00 |
| V2S | sec_cm_fsm_sparse | kmac_sec_cm | 1.756m | 58.422ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ctr_redun | kmac_sec_cm | 1.756m | 58.422ms | 5 | 5 | 100.00 |
| V2S | sec_cm_packer_ctr_redun | kmac_sec_cm | 1.756m | 58.422ms | 5 | 5 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_regwen | kmac_smoke | 1.487m | 8.161ms | 50 | 50 | 100.00 |
| V2S | sec_cm_fsm_global_esc | kmac_lc_escalation | 1.205m | 1.169ms | 50 | 50 | 100.00 |
| V2S | sec_cm_fsm_local_esc | kmac_sec_cm | 1.756m | 58.422ms | 5 | 5 | 100.00 |
| V2S | sec_cm_absorbed_ctrl_mubi | kmac_mubi | 5.720m | 12.464ms | 10 | 10 | 100.00 |
| V2S | sec_cm_sw_cmd_ctrl_sparse | kmac_smoke | 1.487m | 8.161ms | 50 | 50 | 100.00 |
| V2S | TOTAL | 75 | 75 | 100.00 | |||
| V3 | throughput | kmac_throughput | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | kmac_stress_all_with_rand_reset | 5.293m | 5.429ms | 2 | 10 | 20.00 |
| V3 | TOTAL | 2 | 10 | 20.00 | |||
| TOTAL | 881 | 890 | 98.99 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 8 | 100.00 |
| V2 | 25 | 25 | 24 | 96.00 |
| V2S | 5 | 5 | 5 | 100.00 |
| V3 | 2 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 92.40 | 95.89 | 92.27 | 100.00 | 69.42 | 94.11 | 98.84 | 96.29 |
UVM_ERROR (kmac_scoreboard.sv:1196) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 6 failures:
1.kmac_stress_all_with_rand_reset.36708883973215815759981519955748250924989112358828675513311163950196290807573
Line 397, in log /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 6669777868 ps: (kmac_scoreboard.sv:1196) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483736 [0x80000058]) reg name: kmac_reg_block.err_code
UVM_INFO @ 6669777868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.kmac_stress_all_with_rand_reset.94290326877252331542661348605799003334157676348030026039912099373008773120803
Line 822, in log /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2385797664 ps: (kmac_scoreboard.sv:1196) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483688 [0x80000028]) reg name: kmac_reg_block.err_code
UVM_INFO @ 2385797664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_ERROR (cip_base_vseq.sv:867) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
2.kmac_stress_all_with_rand_reset.111799690316452285900516298995564303666461452986088045727878069579322568005412
Line 449, in log /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 6073686565 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 6073686565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.kmac_stress_all_with_rand_reset.33722415972749694744984427231894062729728005106423354866210470235344045391190
Line 105, in log /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/6.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5642819158 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5642819158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (kmac_base_vseq.sv:382) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set! has 1 failures:
35.kmac_key_error.110994354820230815196608551163742559864543324383006590435476006885253341835843
Line 70, in log /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/35.kmac_key_error/latest/run.log
UVM_ERROR @ 785671538 ps: (kmac_base_vseq.sv:382) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
UVM_INFO @ 785671538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---