KMAC/UNMASKED Simulation Results

Monday September 09 2024 02:20:26 UTC

GitHub Revision: `af2d1709f9`

Branch: os_regression_2024_09_08

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 13980492992314588037778262839223440914483141513139750793389284041724730149540

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.855m	19.864ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.850s	107.061us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.930s	126.261us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	26.820s	20.467ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.040s	140.266us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.850s	300.915us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.930s	126.261us	20	20	100.00
		kmac_csr_aliasing	10.040s	140.266us	5	5	100.00
V1	mem_walk	kmac_mem_walk	1.180s	13.950us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.990s	37.341us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	1.241h	130.443ms	50	50	100.00
V2	burst_write	kmac_burst_write	21.086m	286.769ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	40.581m	315.145ms	5	5	100.00
		kmac_test_vectors_sha3_256	37.723m	608.112ms	5	5	100.00
		kmac_test_vectors_sha3_384	35.069m	417.599ms	5	5	100.00
		kmac_test_vectors_sha3_512	22.160m	70.904ms	5	5	100.00
		kmac_test_vectors_shake_128	51.814m	75.874ms	5	5	100.00
		kmac_test_vectors_shake_256	38.698m	1.083s	5	5	100.00
		kmac_test_vectors_kmac	4.690s	226.776us	5	5	100.00
		kmac_test_vectors_kmac_xof	3.610s	238.717us	5	5	100.00
V2	sideload	kmac_sideload	7.063m	18.770ms	50	50	100.00
V2	app	kmac_app	6.899m	23.630ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.175m	16.706ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	8.557m	136.360ms	50	50	100.00
V2	error	kmac_error	9.224m	33.669ms	50	50	100.00
V2	key_error	kmac_key_error	18.800s	10.526ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	55.680s	2.805ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	54.850s	22.616ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	49.090s	5.884ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	37.600s	1.127ms	50	50	100.00
V2	stress_all	kmac_stress_all	39.798m	180.127ms	50	50	100.00
V2	intr_test	kmac_intr_test	1.250s	32.944us	50	50	100.00
V2	alert_test	kmac_alert_test	1.350s	35.772us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	5.180s	1.420ms	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	5.180s	1.420ms	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.850s	107.061us	5	5	100.00
		kmac_csr_rw	1.930s	126.261us	20	20	100.00
		kmac_csr_aliasing	10.040s	140.266us	5	5	100.00
		kmac_same_csr_outstanding	3.320s	359.405us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.850s	107.061us	5	5	100.00
		kmac_csr_rw	1.930s	126.261us	20	20	100.00
		kmac_csr_aliasing	10.040s	140.266us	5	5	100.00
		kmac_same_csr_outstanding	3.320s	359.405us	20	20	100.00
V2		TOTAL			689	690	99.86
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.200s	83.067us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.200s	83.067us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.200s	83.067us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.200s	83.067us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.810s	238.632us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.945m	28.779ms	5	5	100.00
		kmac_tl_intg_err	6.950s	519.982us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	6.950s	519.982us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	37.600s	1.127ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.855m	19.864ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.063m	18.770ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.200s	83.067us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.945m	28.779ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.945m	28.779ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.945m	28.779ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.855m	19.864ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	37.600s	1.127ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.945m	28.779ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	8.878m	16.791ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.855m	19.864ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	5.827m	18.747ms	6	10	60.00
V3		TOTAL			6	10	60.00
		TOTAL			885	890	99.44

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	24	96.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.25	95.89	92.30	100.00	68.60	94.11	98.84	96.01

Failure Buckets

UVM_ERROR (kmac_scoreboard.sv:1196) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 4 failures:
- Test kmac_stress_all_with_rand_reset has 4 failures.
  - 0.kmac_stress_all_with_rand_reset.114955260580381494802642407113545377093839065909327194276351470785305711273989
    Line 184, in log /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 549380618 ps: (kmac_scoreboard.sv:1196) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483768 [0x80000078]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 549380618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.kmac_stress_all_with_rand_reset.104307530897793018053289330024950586352399466899094765850602823726644511340099
    Line 761, in log /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1656409401 ps: (kmac_scoreboard.sv:1196) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483680 [0x80000020]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 1656409401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_burst_write has 1 failures.
  - 44.kmac_burst_write.51408946438531404241623720072304272732039241205266845372425972507030455694061
    Line 865, in log /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/44.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

KMAC/UNMASKED Simulation Results

Monday September 09 2024 02:20:26 UTC

GitHub Revision: af2d1709f9

Branch: os_regression_2024_09_08

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 13980492992314588037778262839223440914483141513139750793389284041724730149540

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `af2d1709f9`