LC_CTRL Simulation Results

Sunday May 28 2023 07:05:15 UTC

GitHub Revision: `c06cc3921`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 2869101736

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	10.860s	1.361ms	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.070s	50.262us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.120s	54.745us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.700s	56.017us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.710s	126.537us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.860s	70.443us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.120s	54.745us	20	20	100.00
		lc_ctrl_csr_aliasing	1.710s	126.537us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	13.640s	378.885us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	25.630s	399.713us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.930s	10.040us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.290s	116.937us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	1.083m	1.530ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	28.450s	3.999ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	1.083m	1.530ms	50	50	100.00
		lc_ctrl_prog_failure	5.290s	116.937us	50	50	100.00
		lc_ctrl_errors	28.450s	3.999ms	50	50	100.00
		lc_ctrl_security_escalation	16.220s	9.981ms	50	50	100.00
		lc_ctrl_jtag_state_failure	2.422m	4.683ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	31.450s	1.229ms	20	20	100.00
		lc_ctrl_jtag_errors	2.242m	5.201ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	19.110s	784.312us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	45.200s	1.396ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	31.450s	1.229ms	20	20	100.00
		lc_ctrl_jtag_errors	2.242m	5.201ms	20	20	100.00
		lc_ctrl_jtag_access	28.620s	1.292ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	23.470s	970.586us	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	6.510s	280.702us	10	10	100.00
		lc_ctrl_jtag_csr_rw	4.220s	182.149us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	50.580s	2.658ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	15.240s	1.418ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.930s	527.867us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	2.690s	74.345us	9	10	90.00
		lc_ctrl_jtag_alert_test	3.910s	159.521us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	39.490s	1.925ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.330s	84.863us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	8.091m	17.249ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.300s	53.538us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.810s	304.128us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.810s	304.128us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.070s	50.262us	5	5	100.00
		lc_ctrl_csr_rw	1.120s	54.745us	20	20	100.00
		lc_ctrl_csr_aliasing	1.710s	126.537us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.900s	188.067us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.070s	50.262us	5	5	100.00
		lc_ctrl_csr_rw	1.120s	54.745us	20	20	100.00
		lc_ctrl_csr_aliasing	1.710s	126.537us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.900s	188.067us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	1.044m	204.251us	5	5	100.00
		lc_ctrl_tl_intg_err	4.160s	1.401ms	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.160s	1.401ms	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	25.630s	399.713us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	1.083m	1.530ms	50	50	100.00
		lc_ctrl_sec_cm	1.044m	204.251us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	1.083m	1.530ms	50	50	100.00
		lc_ctrl_sec_cm	1.044m	204.251us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	1.083m	1.530ms	50	50	100.00
		lc_ctrl_sec_cm	1.044m	204.251us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	1.083m	1.530ms	50	50	100.00
		lc_ctrl_sec_cm	1.044m	204.251us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	1.083m	1.530ms	50	50	100.00
		lc_ctrl_sec_cm	1.044m	204.251us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	1.083m	1.530ms	50	50	100.00
		lc_ctrl_sec_cm	1.044m	204.251us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	1.083m	1.530ms	50	50	100.00
		lc_ctrl_sec_cm	1.044m	204.251us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	1.083m	1.530ms	50	50	100.00
		lc_ctrl_sec_cm	1.044m	204.251us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.220s	9.981ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	13.640s	378.885us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	45.200s	1.396ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	22.680s	2.337ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	22.680s	2.337ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	24.660s	1.019ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	17.440s	552.702us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	17.440s	552.702us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	16.069m	108.501ms	3	50	6.00
V3		TOTAL			3	50	6.00
		TOTAL			982	1030	95.34

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.16	97.18	94.81	91.98	100.00	95.67	98.48	95.00

Failure Buckets

Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 28 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 28 failures.
  - 0.lc_ctrl_stress_all_with_rand_reset.905467594
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:03c40ef8-e0c1-40f4-9194-bb0f258d6392
```
  - 1.lc_ctrl_stress_all_with_rand_reset.3838023216
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:11ad6bb9-d93e-41a2-ac0e-a3f1216f743b
```
  - ... and 26 more failures.
Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 6 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 6 failures.
  - 2.lc_ctrl_stress_all_with_rand_reset.2589806958
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:1ff0f9a2-9936-400a-ba29-9e473647e992
```
  - 23.lc_ctrl_stress_all_with_rand_reset.3195489678
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/23.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:96145a04-f203-4876-a046-865de0d348d9
```
  - ... and 4 more failures.

UVM_FATAL (lc_ctrl_scoreboard.sv:265) scoreboard [scoreboard] Access unexpected addr * has 5 failures:

Test lc_ctrl_stress_all_with_rand_reset has 5 failures.

10.lc_ctrl_stress_all_with_rand_reset.1903969476
Line 4832, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/10.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 4872525931 ps: (lc_ctrl_scoreboard.sv:265) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0x5e72be00
  UVM_INFO @ 4872525931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

13.lc_ctrl_stress_all_with_rand_reset.1582136483
Line 9237, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/13.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 3890579544 ps: (lc_ctrl_scoreboard.sv:265) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0x4dab3200
  UVM_INFO @ 3890579544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (jtag_riscv_monitor.sv:80) monitor [monitor] Bad status - DmiReserved(*) has 3 failures:

Test lc_ctrl_jtag_csr_mem_rw_with_rand_reset has 1 failures.

1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.535179952
Line 306, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @   2655231 ps: (jtag_riscv_monitor.sv:80) uvm_test_top.env.m_jtag_riscv_agent.monitor [uvm_test_top.env.m_jtag_riscv_agent.monitor] Bad status - DmiReserved(0x1)
  UVM_INFO @   2655231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

5.lc_ctrl_stress_all_with_rand_reset.185630867
Line 8253, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 5481575426 ps: (jtag_riscv_monitor.sv:80) uvm_test_top.env.m_jtag_riscv_agent.monitor [uvm_test_top.env.m_jtag_riscv_agent.monitor] Bad status - DmiReserved(0x1)
  UVM_INFO @ 5481575426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

25.lc_ctrl_stress_all_with_rand_reset.4129615018
Line 1712, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/25.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1625564192 ps: (jtag_riscv_monitor.sv:80) uvm_test_top.env.m_jtag_riscv_agent.monitor [uvm_test_top.env.m_jtag_riscv_agent.monitor] Bad status - DmiReserved(0x1)
  UVM_INFO @ 1625564192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: lc_ctrl_reg_block.status.ready reset value: * called from ../src/lowrisc_dv_lc_ctrl_env_*/seq_lib/lc_ctrl_errors_vseq.sv: * has 2 failures:

Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

9.lc_ctrl_stress_all_with_rand_reset.3696957776
Line 4747, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/9.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3308915580 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: lc_ctrl_reg_block.status.ready reset value: 0x0 called from ../src/lowrisc_dv_lc_ctrl_env_0.1/seq_lib/lc_ctrl_errors_vseq.sv: 290
  UVM_INFO @ 3308915580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

38.lc_ctrl_stress_all_with_rand_reset.2582326297
Line 3854, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/38.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 9550948385 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: lc_ctrl_reg_block.status.ready reset value: 0x0 called from ../src/lowrisc_dv_lc_ctrl_env_0.1/seq_lib/lc_ctrl_errors_vseq.sv: 290
  UVM_INFO @ 9550948385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: lc_ctrl_reg_block.transition_token_* reset value: * has 2 failures:

Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

12.lc_ctrl_stress_all_with_rand_reset.845119700
Line 20649, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/12.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 47851448104 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 3618958631 [0xd7b4ed27]) Regname: lc_ctrl_reg_block.transition_token_3 reset value: 0x0
  UVM_INFO @ 47851448104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

42.lc_ctrl_stress_all_with_rand_reset.2402844888
Line 11026, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/42.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 6698615586 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 3829839773 [0xe446b79d]) Regname: lc_ctrl_reg_block.transition_token_3 reset value: 0x0
  UVM_INFO @ 6698615586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: lc_ctrl_reg_block.otp_vendor_test_ctrl reset value: * has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 18.lc_ctrl_stress_all_with_rand_reset.4174762502
    Line 314, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/18.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1146031693 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 3842502781 [0xe507f07d]) Regname: lc_ctrl_reg_block.otp_vendor_test_ctrl reset value: 0x0
  UVM_INFO @ 1146031693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:519) [lc_ctrl_smoke_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_prog_error fired unexpectedly! has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 48.lc_ctrl_stress_all_with_rand_reset.1158902062
    Line 18602, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/48.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 68325833937 ps: (cip_base_vseq.sv:519) [uvm_test_top.env.virtual_sequencer.lc_ctrl_smoke_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_prog_error fired unexpectedly!
  UVM_INFO @ 68325833937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```