LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Tuesday May 07 2024 19:02:25 UTC

GitHub Revision: 18c8953cf1

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 23463731882259624708557902606691160899163550314542713462365308032920382521803

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	7.450s	973.297us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.020s	91.376us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.190s	17.946us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	3.000s	169.378us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.360s	23.749us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.250s	33.236us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.190s	17.946us	20	20	100.00
		lc_ctrl_csr_aliasing	1.360s	23.749us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.910s	145.894us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	25.860s	383.963us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.980s	24.232us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.340s	146.147us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	34.430s	1.406ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	18.940s	2.157ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	34.430s	1.406ms	50	50	100.00
		lc_ctrl_prog_failure	5.340s	146.147us	50	50	100.00
		lc_ctrl_errors	18.940s	2.157ms	50	50	100.00
		lc_ctrl_security_escalation	14.500s	1.603ms	50	50	100.00
		lc_ctrl_jtag_state_failure	2.147m	4.195ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	19.550s	2.984ms	20	20	100.00
		lc_ctrl_jtag_errors	1.566m	13.962ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	16.000s	1.183ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	22.410s	2.583ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	19.550s	2.984ms	20	20	100.00
		lc_ctrl_jtag_errors	1.566m	13.962ms	20	20	100.00
		lc_ctrl_jtag_access	28.600s	15.149ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	45.210s	9.469ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	5.030s	193.452us	10	10	100.00
		lc_ctrl_jtag_csr_rw	1.990s	59.708us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	49.700s	9.457ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	10.700s	2.476ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.400s	45.988us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	6.860s	280.837us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.510s	79.785us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	1.645m	4.311ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.460s	26.899us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	7.365m	56.717ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.410s	30.620us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.420s	364.710us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.420s	364.710us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.020s	91.376us	5	5	100.00
		lc_ctrl_csr_rw	1.190s	17.946us	20	20	100.00
		lc_ctrl_csr_aliasing	1.360s	23.749us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.900s	97.519us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.020s	91.376us	5	5	100.00
		lc_ctrl_csr_rw	1.190s	17.946us	20	20	100.00
		lc_ctrl_csr_aliasing	1.360s	23.749us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.900s	97.519us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	39.190s	836.006us	5	5	100.00
		lc_ctrl_tl_intg_err	4.610s	270.686us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.610s	270.686us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	25.860s	383.963us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	34.430s	1.406ms	50	50	100.00
		lc_ctrl_sec_cm	39.190s	836.006us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	34.430s	1.406ms	50	50	100.00
		lc_ctrl_sec_cm	39.190s	836.006us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	34.430s	1.406ms	50	50	100.00
		lc_ctrl_sec_cm	39.190s	836.006us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	34.430s	1.406ms	50	50	100.00
		lc_ctrl_sec_cm	39.190s	836.006us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	34.430s	1.406ms	50	50	100.00
		lc_ctrl_sec_cm	39.190s	836.006us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	34.430s	1.406ms	50	50	100.00
		lc_ctrl_sec_cm	39.190s	836.006us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	34.430s	1.406ms	50	50	100.00
		lc_ctrl_sec_cm	39.190s	836.006us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	34.430s	1.406ms	50	50	100.00
		lc_ctrl_sec_cm	39.190s	836.006us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	14.500s	1.603ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.910s	145.894us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	22.410s	2.583ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	18.810s	838.610us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	18.810s	838.610us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	23.730s	911.173us	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	18.930s	536.292us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	18.930s	536.292us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.260h	65.816ms	22	50	44.00
V3		TOTAL			22	50	44.00
		TOTAL			1002	1030	97.28

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.89	97.82	96.03	93.31	97.62	98.52	98.51	96.47

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 23 failures.

    • 2.lc_ctrl_stress_all_with_rand_reset.22746910469486841254474840075182655810330389953811302514123917557689173037660
      Line 3898, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 35052527888 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 35052527888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.lc_ctrl_stress_all_with_rand_reset.115379319865845769755629960184874441163157493678269287025083520339671899817384
      Line 24103, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 146418528664 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 146418528664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 21 more failures.

• Error-[CNST-STOF] Constraint solver timeout failure has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 37.lc_ctrl_stress_all_with_rand_reset.74152179665641655786459505261716037756325188185178914477865258591840783319535
      Line 35193, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • 42.lc_ctrl_stress_all_with_rand_reset.48682126460566575730332297491507407133595632195271275468823579887079796043217
      Line 48561, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 5.lc_ctrl_stress_all_with_rand_reset.898468138906670160850727399896913061087860703160350046377458379620861674284
      Line 34656, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 19436367777 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 19436367777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_smoke_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_prog_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 16.lc_ctrl_stress_all_with_rand_reset.72437018622341294348225539907412327872745254629379636089758037687147588082980
      Line 4442, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 978504003 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_smoke_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_prog_error fired unexpectedly!
        UVM_INFO @ 978504003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 39.lc_ctrl_stress_all_with_rand_reset.102806205169953770446504904816699087286534807816841594365120072666204561638781
      Line 18685, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 12937607064 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 12937607064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.05.06_04.56.29
• 2024.05.03_05.11.54
• 2024.05.01_04.23.04
• 2024.04.29_07.59.43
• 2024.04.26_07.49.06
• 2024.04.24_08.00.56
• 2024.04.22_07.24.48