LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Thursday May 09 2024 19:02:32 UTC

GitHub Revision: 9656691e03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 30170103562476460183108208532025718695603957360441815475011549460912256789439

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	7.620s	177.943us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.240s	31.581us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.170s	19.437us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.030s	178.671us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.350s	126.386us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.070s	59.773us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.170s	19.437us	20	20	100.00
		lc_ctrl_csr_aliasing	1.350s	126.386us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.570s	163.743us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	20.640s	1.240ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.990s	12.362us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.540s	467.538us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	36.470s	413.497us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	21.050s	930.796us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	36.470s	413.497us	50	50	100.00
		lc_ctrl_prog_failure	4.540s	467.538us	50	50	100.00
		lc_ctrl_errors	21.050s	930.796us	50	50	100.00
		lc_ctrl_security_escalation	15.340s	602.785us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.717m	7.112ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	22.620s	3.594ms	20	20	100.00
		lc_ctrl_jtag_errors	1.229m	5.072ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	10.370s	743.953us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	26.670s	2.768ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	22.620s	3.594ms	20	20	100.00
		lc_ctrl_jtag_errors	1.229m	5.072ms	20	20	100.00
		lc_ctrl_jtag_access	32.050s	1.537ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	34.010s	1.258ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.790s	579.160us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.050s	344.703us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	16.850s	673.294us	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	22.950s	3.919ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.810s	37.551us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	6.750s	1.107ms	10	10	100.00
		lc_ctrl_jtag_alert_test	3.330s	231.571us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	48.150s	9.143ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.280s	64.477us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	10.546m	79.820ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.430s	26.370us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.090s	105.459us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.090s	105.459us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.240s	31.581us	5	5	100.00
		lc_ctrl_csr_rw	1.170s	19.437us	20	20	100.00
		lc_ctrl_csr_aliasing	1.350s	126.386us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.980s	42.491us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.240s	31.581us	5	5	100.00
		lc_ctrl_csr_rw	1.170s	19.437us	20	20	100.00
		lc_ctrl_csr_aliasing	1.350s	126.386us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.980s	42.491us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	41.190s	534.256us	5	5	100.00
		lc_ctrl_tl_intg_err	4.290s	117.195us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.290s	117.195us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	20.640s	1.240ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	36.470s	413.497us	50	50	100.00
		lc_ctrl_sec_cm	41.190s	534.256us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	36.470s	413.497us	50	50	100.00
		lc_ctrl_sec_cm	41.190s	534.256us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	36.470s	413.497us	50	50	100.00
		lc_ctrl_sec_cm	41.190s	534.256us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	36.470s	413.497us	50	50	100.00
		lc_ctrl_sec_cm	41.190s	534.256us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	36.470s	413.497us	50	50	100.00
		lc_ctrl_sec_cm	41.190s	534.256us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	36.470s	413.497us	50	50	100.00
		lc_ctrl_sec_cm	41.190s	534.256us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	36.470s	413.497us	50	50	100.00
		lc_ctrl_sec_cm	41.190s	534.256us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	36.470s	413.497us	50	50	100.00
		lc_ctrl_sec_cm	41.190s	534.256us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	15.340s	602.785us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.570s	163.743us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	26.670s	2.768ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	19.010s	764.534us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	19.010s	764.534us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	21.600s	2.436ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	21.480s	3.336ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	21.480s	3.336ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	2.682h	41.296ms	22	50	44.00
V3		TOTAL			22	50	44.00
		TOTAL			1001	1030	97.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.79	97.82	95.38	93.31	97.62	98.52	98.76	96.11

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 20 failures.

    • 2.lc_ctrl_stress_all_with_rand_reset.111699215589310390807948587922938306577693631801579104794791664002310552982361
      Line 866, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 801083036 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 801083036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.lc_ctrl_stress_all_with_rand_reset.4410605214561823406007240502744415723855174020579511642425623129185842364486
      Line 7805, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5067067469 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 5067067469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 18 more failures.

• Error-[CNST-STOF] Constraint solver timeout failure has 4 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 4 failures.

    • 10.lc_ctrl_stress_all_with_rand_reset.88695741838037226983254745542946893751075652028490140083203081023802531848293
      Line 54904, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • 19.lc_ctrl_stress_all_with_rand_reset.94263300934503739823869440489285439292519086109560722958904377917598834943315
      Line 35255, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • ... and 2 more failures.

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.26438761581175399403558235467651617880278361266827496267598522402689519875055
      Line 28514, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 43633229494 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 43633229494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 49.lc_ctrl_stress_all_with_rand_reset.32809574228308693776649332432766649215115701700176574890848423881412960462647
      Line 14172, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 30347449252 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 30347449252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_smoke_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_prog_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 31.lc_ctrl_stress_all_with_rand_reset.95430960005289687042263598667718239035878376333122858739791571367334493330869
      Line 777, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 380539086 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_smoke_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_prog_error fired unexpectedly!
        UVM_INFO @ 380539086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_stress_all has 1 failures.

    • 33.lc_ctrl_stress_all.103079263281827982793542016691477672641343554121106214009438926424290170290850
      Line 2023, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 181306754 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 181306754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 42.lc_ctrl_stress_all_with_rand_reset.25549767661359894861422512127905982455636620940787522007058150256218963263245
      Line 42871, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 31285773286 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 31285773286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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