LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Sunday May 12 2024 19:02:35 UTC

GitHub Revision: 69c572b503

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 72674276607041733394622960695970595070180537542023880499199659375034056632550

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	6.090s	85.441us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.030s	28.335us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.180s	16.731us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.780s	205.941us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.790s	37.409us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.660s	26.537us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.180s	16.731us	20	20	100.00
		lc_ctrl_csr_aliasing	1.790s	37.409us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	11.230s	254.035us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	26.320s	1.196ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.990s	14.105us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.800s	210.234us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	40.980s	783.009us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	20.670s	1.806ms	49	50	98.00
V2	security_escalation	lc_ctrl_state_failure	40.980s	783.009us	50	50	100.00
		lc_ctrl_prog_failure	4.800s	210.234us	50	50	100.00
		lc_ctrl_errors	20.670s	1.806ms	49	50	98.00
		lc_ctrl_security_escalation	15.490s	436.093us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.982m	3.248ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	18.950s	2.345ms	20	20	100.00
		lc_ctrl_jtag_errors	1.153m	8.693ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	15.880s	584.035us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	35.040s	1.161ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	18.950s	2.345ms	20	20	100.00
		lc_ctrl_jtag_errors	1.153m	8.693ms	20	20	100.00
		lc_ctrl_jtag_access	32.310s	1.403ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	35.270s	4.742ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.730s	353.325us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.050s	207.325us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	30.460s	4.143ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	23.080s	1.085ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.840s	142.953us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	3.950s	448.920us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.380s	75.741us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	7.210s	746.507us	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.340s	70.872us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	10.355m	21.095ms	48	50	96.00
V2	alert_test	lc_ctrl_alert_test	1.340s	43.511us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.690s	159.330us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.690s	159.330us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.030s	28.335us	5	5	100.00
		lc_ctrl_csr_rw	1.180s	16.731us	20	20	100.00
		lc_ctrl_csr_aliasing	1.790s	37.409us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.980s	232.889us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.030s	28.335us	5	5	100.00
		lc_ctrl_csr_rw	1.180s	16.731us	20	20	100.00
		lc_ctrl_csr_aliasing	1.790s	37.409us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.980s	232.889us	20	20	100.00
V2		TOTAL			697	700	99.57
V2S	tl_intg_err	lc_ctrl_sec_cm	38.690s	401.499us	5	5	100.00
		lc_ctrl_tl_intg_err	4.160s	103.010us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.160s	103.010us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	26.320s	1.196ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	40.980s	783.009us	50	50	100.00
		lc_ctrl_sec_cm	38.690s	401.499us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	40.980s	783.009us	50	50	100.00
		lc_ctrl_sec_cm	38.690s	401.499us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	40.980s	783.009us	50	50	100.00
		lc_ctrl_sec_cm	38.690s	401.499us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	40.980s	783.009us	50	50	100.00
		lc_ctrl_sec_cm	38.690s	401.499us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	40.980s	783.009us	50	50	100.00
		lc_ctrl_sec_cm	38.690s	401.499us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	40.980s	783.009us	50	50	100.00
		lc_ctrl_sec_cm	38.690s	401.499us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	40.980s	783.009us	50	50	100.00
		lc_ctrl_sec_cm	38.690s	401.499us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	40.980s	783.009us	50	50	100.00
		lc_ctrl_sec_cm	38.690s	401.499us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	15.490s	436.093us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.230s	254.035us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	35.040s	1.161ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	23.370s	608.895us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	23.370s	608.895us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	22.440s	726.132us	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	15.850s	1.391ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	15.850s	1.391ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	38.195m	167.147ms	23	50	46.00
V3		TOTAL			23	50	46.00
		TOTAL			1000	1030	97.09

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	25	92.59
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.18	97.82	95.84	93.31	100.00	98.52	98.51	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 21 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 21 failures.

    • 2.lc_ctrl_stress_all_with_rand_reset.77435989170639670261434450676512537523342732500220903380695736449610856243660
      Line 7644, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 14642777109 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 14642777109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.lc_ctrl_stress_all_with_rand_reset.83882049447815105127980039692405205207425727786664519761153430770918932451493
      Line 12059, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 22618862008 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 22618862008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 19 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 5 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 4 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.92425392044139269804269106248028358542007292280328672181955611947461601569383
      Line 20413, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 41216042492 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 41216042492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.lc_ctrl_stress_all_with_rand_reset.21509554455857809439743359017328129272214705909210158360214138510294410442951
      Line 18279, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 120815712204 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 120815712204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 2 more failures.

  • Test lc_ctrl_stress_all has 1 failures.

    • 27.lc_ctrl_stress_all.39076663854904052977886630496687054081225935688122363903064042245984298990015
      Line 7515, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 2633628479 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 2633628479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 21.lc_ctrl_stress_all_with_rand_reset.40711547624197400153258971222213288352539041621862977072455638091106107535899
      Line 47253, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_stress_all has 1 failures.

    • 25.lc_ctrl_stress_all.13075888900869051162808307265103718965529360070292157650273108375604374252656
      Line 3098, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 1015937633 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 1015937633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:769) [lc_ctrl_lc_errors_vseq] Check failed otp_error_act == otp_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_errors has 1 failures.

    • 37.lc_ctrl_errors.16721976964248410097968881398704534013481938607627820543958091651637885643599
      Line 3125, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_errors/latest/run.log

        UVM_ERROR @ 548687742 ps: (lc_ctrl_errors_vseq.sv:769) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed otp_error_act == otp_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 548687742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 46.lc_ctrl_stress_all_with_rand_reset.101473030952649846661250378534917421399763976437785667742382717518259982949915
      Line 47613, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 38110693983 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 38110693983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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