LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Tuesday May 14 2024 19:02:33 UTC

GitHub Revision: 00fe426038

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56275124637035941820967954627144971699378360917446801543187025394370981034792

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	11.460s	663.698us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.200s	15.457us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.210s	20.304us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	3.030s	82.072us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.370s	23.612us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.910s	25.227us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.210s	20.304us	20	20	100.00
		lc_ctrl_csr_aliasing	1.370s	23.612us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.960s	338.367us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	17.680s	256.753us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.950s	40.559us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.850s	422.161us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	36.900s	1.485ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	21.660s	7.371ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	36.900s	1.485ms	50	50	100.00
		lc_ctrl_prog_failure	4.850s	422.161us	50	50	100.00
		lc_ctrl_errors	21.660s	7.371ms	50	50	100.00
		lc_ctrl_security_escalation	16.380s	737.773us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.994m	14.495ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	20.050s	679.688us	20	20	100.00
		lc_ctrl_jtag_errors	1.480m	3.217ms	19	20	95.00
V2	jtag_access	lc_ctrl_jtag_smoke	11.770s	424.469us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	23.940s	2.553ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	20.050s	679.688us	20	20	100.00
		lc_ctrl_jtag_errors	1.480m	3.217ms	19	20	95.00
		lc_ctrl_jtag_access	27.230s	1.094ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	36.860s	10.148ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.810s	523.357us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.400s	63.171us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	23.890s	2.011ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	16.100s	2.915ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.170s	49.282us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	3.750s	468.833us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.120s	57.720us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	31.920s	6.277ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.570s	22.258us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	8.287m	29.453ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.650s	35.123us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.980s	625.461us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.980s	625.461us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.200s	15.457us	5	5	100.00
		lc_ctrl_csr_rw	1.210s	20.304us	20	20	100.00
		lc_ctrl_csr_aliasing	1.370s	23.612us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.520s	259.373us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.200s	15.457us	5	5	100.00
		lc_ctrl_csr_rw	1.210s	20.304us	20	20	100.00
		lc_ctrl_csr_aliasing	1.370s	23.612us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.520s	259.373us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	38.520s	891.756us	5	5	100.00
		lc_ctrl_tl_intg_err	5.000s	159.326us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	5.000s	159.326us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	17.680s	256.753us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	36.900s	1.485ms	50	50	100.00
		lc_ctrl_sec_cm	38.520s	891.756us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	36.900s	1.485ms	50	50	100.00
		lc_ctrl_sec_cm	38.520s	891.756us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	36.900s	1.485ms	50	50	100.00
		lc_ctrl_sec_cm	38.520s	891.756us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	36.900s	1.485ms	50	50	100.00
		lc_ctrl_sec_cm	38.520s	891.756us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	36.900s	1.485ms	50	50	100.00
		lc_ctrl_sec_cm	38.520s	891.756us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	36.900s	1.485ms	50	50	100.00
		lc_ctrl_sec_cm	38.520s	891.756us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	36.900s	1.485ms	50	50	100.00
		lc_ctrl_sec_cm	38.520s	891.756us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	36.900s	1.485ms	50	50	100.00
		lc_ctrl_sec_cm	38.520s	891.756us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.380s	737.773us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.960s	338.367us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	23.940s	2.553ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	20.750s	2.141ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	20.750s	2.141ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	20.130s	737.874us	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	18.490s	1.033ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	18.490s	1.033ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	35.800m	44.186ms	21	50	42.00
V3		TOTAL			21	50	42.00
		TOTAL			1000	1030	97.09

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.86	97.82	95.93	93.31	97.62	98.52	98.51	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 26 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 26 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.86148362558126698926023930098477255160974566025963552649489324910954800662843
      Line 8533, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 88969989746 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 88969989746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.lc_ctrl_stress_all_with_rand_reset.4896150160287538725214890767566285702621113053287045950592420320958893251515
      Line 325, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1558016229 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1558016229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 24 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_jtag_errors has 1 failures.

    • 3.lc_ctrl_jtag_errors.85726249317257454623043586835864641327923159298588389761440909866515760869705
      Line 3427, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_errors/latest/run.log

        UVM_ERROR @ 6033536407 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 6033536407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 4.lc_ctrl_stress_all_with_rand_reset.57963128812495230236884592017938854051434047482210855795713839937671130994004
      Line 63665, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_ERROR (cip_base_vseq.sv:753) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 22.lc_ctrl_stress_all_with_rand_reset.89777090294534450413260774661418085473955834794861874185278513980255947562954
      Line 7226, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 41532629237 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 41532629237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job lc_ctrl_volatile_unlock_disabled-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 41.lc_ctrl_stress_all_with_rand_reset.15609197682723943256687908778518430621755724514314405037117457771181748608882
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:d10b4d9b-5e32-4738-a7d0-d9d95b52e07e
      

Past Results

• Latest
• 2024.05.13_03.43.32
• 2024.05.10_04.30.31
• 2024.05.08_03.39.50
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