LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Thursday May 16 2024 19:02:11 UTC

GitHub Revision: 349bab6601

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 60729333463373082946889975499553948547086354767408862399987151421185145065082

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	11.060s	519.098us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.140s	27.983us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.160s	19.085us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.910s	157.184us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.360s	21.992us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.330s	62.650us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.160s	19.085us	20	20	100.00
		lc_ctrl_csr_aliasing	1.360s	21.992us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.060s	95.671us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	23.200s	348.967us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.940s	13.678us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.080s	116.028us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	36.090s	344.181us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	19.910s	5.069ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	36.090s	344.181us	50	50	100.00
		lc_ctrl_prog_failure	5.080s	116.028us	50	50	100.00
		lc_ctrl_errors	19.910s	5.069ms	50	50	100.00
		lc_ctrl_security_escalation	16.100s	452.577us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.575m	3.107ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	12.730s	2.538ms	20	20	100.00
		lc_ctrl_jtag_errors	1.883m	80.371ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	13.600s	529.519us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	25.730s	771.048us	20	20	100.00
		lc_ctrl_jtag_prog_failure	12.730s	2.538ms	20	20	100.00
		lc_ctrl_jtag_errors	1.883m	80.371ms	20	20	100.00
		lc_ctrl_jtag_access	23.970s	2.062ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	34.470s	3.228ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.580s	587.247us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.650s	263.830us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	34.270s	1.474ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	13.840s	571.972us	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.090s	56.342us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	7.030s	273.657us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.190s	502.605us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	18.290s	771.893us	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.090s	22.351us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	11.130m	734.065ms	48	50	96.00
V2	alert_test	lc_ctrl_alert_test	1.580s	37.549us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.070s	1.508ms	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.070s	1.508ms	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.140s	27.983us	5	5	100.00
		lc_ctrl_csr_rw	1.160s	19.085us	20	20	100.00
		lc_ctrl_csr_aliasing	1.360s	21.992us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.930s	48.793us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.140s	27.983us	5	5	100.00
		lc_ctrl_csr_rw	1.160s	19.085us	20	20	100.00
		lc_ctrl_csr_aliasing	1.360s	21.992us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.930s	48.793us	20	20	100.00
V2		TOTAL			698	700	99.71
V2S	tl_intg_err	lc_ctrl_sec_cm	39.590s	244.919us	5	5	100.00
		lc_ctrl_tl_intg_err	5.870s	847.546us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	5.870s	847.546us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	23.200s	348.967us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	36.090s	344.181us	50	50	100.00
		lc_ctrl_sec_cm	39.590s	244.919us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	36.090s	344.181us	50	50	100.00
		lc_ctrl_sec_cm	39.590s	244.919us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	36.090s	344.181us	50	50	100.00
		lc_ctrl_sec_cm	39.590s	244.919us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	36.090s	344.181us	50	50	100.00
		lc_ctrl_sec_cm	39.590s	244.919us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	36.090s	344.181us	50	50	100.00
		lc_ctrl_sec_cm	39.590s	244.919us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	36.090s	344.181us	50	50	100.00
		lc_ctrl_sec_cm	39.590s	244.919us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	36.090s	344.181us	50	50	100.00
		lc_ctrl_sec_cm	39.590s	244.919us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	36.090s	344.181us	50	50	100.00
		lc_ctrl_sec_cm	39.590s	244.919us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.100s	452.577us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.060s	95.671us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	25.730s	771.048us	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	25.350s	586.771us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	25.350s	586.771us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	24.630s	8.030ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	23.230s	3.723ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	23.230s	3.723ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	34.891m	52.407ms	22	50	44.00
V3		TOTAL			22	50	44.00
		TOTAL			1000	1030	97.09

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.92	97.82	96.12	93.31	97.62	98.52	98.76	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 24 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.106770690898539738375174556046017721027928123102167417632788252433254357211782
      Line 13472, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 31894402276 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10004 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 31894402276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.lc_ctrl_stress_all_with_rand_reset.85326582519402727289244421977619430868104011797519248202949971457387566923317
      Line 37245, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 27932733197 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 27932733197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 22 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 4 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.80863929197938831363942571730840148659136740881751696010575359853094665551688
      Line 19326, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 14267912380 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:15000
        UVM_INFO @ 14267912380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 17.lc_ctrl_stress_all_with_rand_reset.110302488175196684889719245159259809436466115809829924826541459036905688645656
      Line 63650, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 160950943573 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 160950943573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_stress_all has 2 failures.

    • 19.lc_ctrl_stress_all.108143179361455809989455755321589857623385210672976845576646166303854684794997
      Line 2707, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 1644130882 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 1644130882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 47.lc_ctrl_stress_all.93780272149818385712963205413461104121641916173892511460062993938879794291262
      Line 9494, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 9215043522 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 9215043522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 26.lc_ctrl_stress_all_with_rand_reset.27748004011676164737884144259135868722751698019108791722960426389077127085415
      Line 28363, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 29968042557 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 29968042557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 41.lc_ctrl_stress_all_with_rand_reset.101285973023413810121499220774771562883059464367960584467013248110679860148654
      Line 44960, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 171804918006 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 171804918006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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