LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Sunday May 19 2024 19:02:23 UTC

GitHub Revision: eb776817a5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56458776725427632834749451790671712939002859133119076946547796163671543192855

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	8.600s	148.751us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.200s	35.373us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.100s	28.393us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.880s	112.387us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.360s	42.270us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.560s	27.017us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.100s	28.393us	20	20	100.00
		lc_ctrl_csr_aliasing	1.360s	42.270us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.840s	686.742us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	21.590s	392.290us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.990s	13.349us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.500s	505.655us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	37.070s	4.839ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	17.680s	1.630ms	49	50	98.00
V2	security_escalation	lc_ctrl_state_failure	37.070s	4.839ms	50	50	100.00
		lc_ctrl_prog_failure	5.500s	505.655us	50	50	100.00
		lc_ctrl_errors	17.680s	1.630ms	49	50	98.00
		lc_ctrl_security_escalation	16.450s	449.059us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.541m	10.135ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	21.520s	1.510ms	20	20	100.00
		lc_ctrl_jtag_errors	1.960m	9.062ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	15.670s	2.563ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	29.560s	785.321us	20	20	100.00
		lc_ctrl_jtag_prog_failure	21.520s	1.510ms	20	20	100.00
		lc_ctrl_jtag_errors	1.960m	9.062ms	20	20	100.00
		lc_ctrl_jtag_access	33.860s	1.446ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	40.610s	1.517ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	2.210s	252.923us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.920s	109.996us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	30.740s	2.945ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	7.830s	1.247ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.490s	23.466us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	2.920s	99.918us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.380s	793.190us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	11.120s	3.901ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.140s	66.442us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	10.952m	83.461ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.330s	49.511us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.490s	152.174us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.490s	152.174us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.200s	35.373us	5	5	100.00
		lc_ctrl_csr_rw	1.100s	28.393us	20	20	100.00
		lc_ctrl_csr_aliasing	1.360s	42.270us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.180s	50.509us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.200s	35.373us	5	5	100.00
		lc_ctrl_csr_rw	1.100s	28.393us	20	20	100.00
		lc_ctrl_csr_aliasing	1.360s	42.270us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.180s	50.509us	20	20	100.00
V2		TOTAL			698	700	99.71
V2S	tl_intg_err	lc_ctrl_sec_cm	38.610s	211.477us	5	5	100.00
		lc_ctrl_tl_intg_err	4.500s	257.755us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.500s	257.755us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	21.590s	392.290us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	37.070s	4.839ms	50	50	100.00
		lc_ctrl_sec_cm	38.610s	211.477us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	37.070s	4.839ms	50	50	100.00
		lc_ctrl_sec_cm	38.610s	211.477us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	37.070s	4.839ms	50	50	100.00
		lc_ctrl_sec_cm	38.610s	211.477us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	37.070s	4.839ms	50	50	100.00
		lc_ctrl_sec_cm	38.610s	211.477us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	37.070s	4.839ms	50	50	100.00
		lc_ctrl_sec_cm	38.610s	211.477us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	37.070s	4.839ms	50	50	100.00
		lc_ctrl_sec_cm	38.610s	211.477us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	37.070s	4.839ms	50	50	100.00
		lc_ctrl_sec_cm	38.610s	211.477us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	37.070s	4.839ms	50	50	100.00
		lc_ctrl_sec_cm	38.610s	211.477us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.450s	449.059us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.840s	686.742us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	29.560s	785.321us	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	23.730s	8.016ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	23.730s	8.016ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	23.290s	3.643ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	18.060s	717.815us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	18.060s	717.815us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	28.499m	56.311ms	22	50	44.00
V3		TOTAL			22	50	44.00
		TOTAL			1000	1030	97.09

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	25	92.59
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.18	97.82	95.93	93.31	100.00	98.52	98.76	95.94

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 21 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 21 failures.

    • 6.lc_ctrl_stress_all_with_rand_reset.92653881832731874859911391136513238376937964389495442802749928077081581361126
      Line 3592, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 8956426474 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 8956426474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 9.lc_ctrl_stress_all_with_rand_reset.42698339448134736220525296617012075781589328718570956979168638226655709966639
      Line 325, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 220982714 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 220982714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 19 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 3 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.83991304503226553089893399466542997953590457313974544820788312703868347252622
      Line 8909, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 27137518698 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 27137518698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 30.lc_ctrl_stress_all_with_rand_reset.62154712086757663975892254646909455247052400894761280603487360217381251973964
      Line 15788, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 21487713727 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 21487713727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_stress_all has 1 failures.

    • 24.lc_ctrl_stress_all.29590742109603613474129497526951613338360769530772503924708828392874587409193
      Line 11768, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 243767557840 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 243767557840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 3 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 2.lc_ctrl_stress_all_with_rand_reset.91467443556922708120533572423342771462846698731843842189658210968820750368159
      Line 43352, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 42169710155 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 42169710155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.lc_ctrl_stress_all_with_rand_reset.72228618246443025912389615472028891838948388766214164573096149999153813421989
      Line 23575, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 13786523260 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 13786523260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• Error-[CNST-STOF] Constraint solver timeout failure has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 5.lc_ctrl_stress_all_with_rand_reset.100558398827611464630579327354213297121550782914541078117601284120583502073825
      Line 34037, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • 25.lc_ctrl_stress_all_with_rand_reset.13234408455496986792110824976031960267138560445577685233066226401126488607265
      Line 41510, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_errors has 1 failures.

    • 29.lc_ctrl_errors.18089872479657371917487902745619131232683182368348579498787720153226793408685
      Line 2915, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_errors/latest/run.log

        UVM_ERROR @ 184254921 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 184254921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.05.17_06.26.17
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• 2024.05.13_03.43.32
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