LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Tuesday May 21 2024 19:02:35 UTC

GitHub Revision: be3d980075

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85829748320245376283659198434338498577935164172956485671224275001047693479661

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	5.430s	849.313us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.290s	22.944us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.110s	17.306us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.670s	27.522us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.680s	105.117us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.400s	127.072us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.110s	17.306us	20	20	100.00
		lc_ctrl_csr_aliasing	1.680s	105.117us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.940s	83.524us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	26.320s	2.200ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.920s	71.189us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.820s	541.242us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	36.750s	342.839us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	27.400s	1.453ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	36.750s	342.839us	50	50	100.00
		lc_ctrl_prog_failure	5.820s	541.242us	50	50	100.00
		lc_ctrl_errors	27.400s	1.453ms	50	50	100.00
		lc_ctrl_security_escalation	16.700s	405.332us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.393m	24.434ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	25.600s	7.332ms	20	20	100.00
		lc_ctrl_jtag_errors	58.550s	7.735ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	13.780s	3.419ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	29.540s	976.824us	20	20	100.00
		lc_ctrl_jtag_prog_failure	25.600s	7.332ms	20	20	100.00
		lc_ctrl_jtag_errors	58.550s	7.735ms	20	20	100.00
		lc_ctrl_jtag_access	25.620s	1.084ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	37.960s	7.862ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	5.440s	1.051ms	10	10	100.00
		lc_ctrl_jtag_csr_rw	4.150s	2.014ms	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	43.500s	4.017ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	27.350s	1.272ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.890s	162.245us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	5.110s	379.817us	10	10	100.00
		lc_ctrl_jtag_alert_test	1.860s	181.172us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	18.830s	792.216us	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.190s	107.779us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	12.636m	104.200ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.500s	293.000us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.790s	129.513us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.790s	129.513us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.290s	22.944us	5	5	100.00
		lc_ctrl_csr_rw	1.110s	17.306us	20	20	100.00
		lc_ctrl_csr_aliasing	1.680s	105.117us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.920s	416.094us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.290s	22.944us	5	5	100.00
		lc_ctrl_csr_rw	1.110s	17.306us	20	20	100.00
		lc_ctrl_csr_aliasing	1.680s	105.117us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.920s	416.094us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	41.350s	1.678ms	5	5	100.00
		lc_ctrl_tl_intg_err	4.420s	297.816us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.420s	297.816us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	26.320s	2.200ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	36.750s	342.839us	50	50	100.00
		lc_ctrl_sec_cm	41.350s	1.678ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	36.750s	342.839us	50	50	100.00
		lc_ctrl_sec_cm	41.350s	1.678ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	36.750s	342.839us	50	50	100.00
		lc_ctrl_sec_cm	41.350s	1.678ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	36.750s	342.839us	50	50	100.00
		lc_ctrl_sec_cm	41.350s	1.678ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	36.750s	342.839us	50	50	100.00
		lc_ctrl_sec_cm	41.350s	1.678ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	36.750s	342.839us	50	50	100.00
		lc_ctrl_sec_cm	41.350s	1.678ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	36.750s	342.839us	50	50	100.00
		lc_ctrl_sec_cm	41.350s	1.678ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	36.750s	342.839us	50	50	100.00
		lc_ctrl_sec_cm	41.350s	1.678ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.700s	405.332us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.940s	83.524us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	29.540s	976.824us	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	22.950s	561.067us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	22.950s	561.067us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	23.270s	3.352ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	16.820s	1.160ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	16.820s	1.160ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	47.667m	134.977ms	27	50	54.00
V3		TOTAL			27	50	54.00
		TOTAL			1007	1030	97.77

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.93	97.82	96.21	93.31	97.62	98.52	98.76	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 19 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 19 failures.

    • 3.lc_ctrl_stress_all_with_rand_reset.16730017252062678590205692949763577571285817915488249329315988047506046286017
      Line 33107, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 78034959616 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 78034959616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.lc_ctrl_stress_all_with_rand_reset.29939669594948171045241501328177385289041204425764101209077939983943615898328
      Line 4166, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6991244837 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 6991244837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 17 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.112759729423787724776663076732491241473926803935867378585740799108638311848977
      Line 4816, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2085010595 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 2085010595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 2.lc_ctrl_stress_all_with_rand_reset.23458027230549290654202282864590362562610269692111524445161642685564577158440
      Line 33647, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 40882783092 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 40882783092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_smoke_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_prog_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 16.lc_ctrl_stress_all_with_rand_reset.86371975164998523677068529045449332656281622316972334408774458660303160214419
      Line 4862, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3725937616 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_smoke_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_prog_error fired unexpectedly!
        UVM_INFO @ 3725937616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 49.lc_ctrl_stress_all_with_rand_reset.90747510800210473562668862281267647051034260989396261906336743120117734383338
      Line 41012, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

Past Results

• Latest
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