LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Thursday May 23 2024 19:02:32 UTC

GitHub Revision: 1579f6a912

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107680075914347604077716278187232582575581754843183664337576824686885697334979

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	9.980s	1.064ms	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.180s	31.572us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.190s	19.774us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.710s	266.146us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.340s	72.306us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.090s	54.689us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.190s	19.774us	20	20	100.00
		lc_ctrl_csr_aliasing	1.340s	72.306us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.080s	98.530us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	21.660s	629.603us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.010s	13.384us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	3.980s	116.573us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	36.030s	226.621us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	28.060s	738.288us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	36.030s	226.621us	50	50	100.00
		lc_ctrl_prog_failure	3.980s	116.573us	50	50	100.00
		lc_ctrl_errors	28.060s	738.288us	50	50	100.00
		lc_ctrl_security_escalation	15.810s	429.406us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.349m	14.309ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	15.880s	1.350ms	20	20	100.00
		lc_ctrl_jtag_errors	1.791m	7.994ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	13.360s	1.016ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	23.750s	3.698ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	15.880s	1.350ms	20	20	100.00
		lc_ctrl_jtag_errors	1.791m	7.994ms	20	20	100.00
		lc_ctrl_jtag_access	30.190s	5.097ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	29.340s	2.129ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	5.330s	2.239ms	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.500s	641.983us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	25.340s	9.244ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	13.950s	577.330us	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.430s	51.423us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.510s	148.228us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.480s	328.729us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	23.970s	1.858ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.150s	14.976us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	10.471m	134.372ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.290s	35.044us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.780s	131.166us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.780s	131.166us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.180s	31.572us	5	5	100.00
		lc_ctrl_csr_rw	1.190s	19.774us	20	20	100.00
		lc_ctrl_csr_aliasing	1.340s	72.306us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.520s	22.057us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.180s	31.572us	5	5	100.00
		lc_ctrl_csr_rw	1.190s	19.774us	20	20	100.00
		lc_ctrl_csr_aliasing	1.340s	72.306us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.520s	22.057us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	41.490s	1.077ms	5	5	100.00
		lc_ctrl_tl_intg_err	4.320s	107.562us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.320s	107.562us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	21.660s	629.603us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	36.030s	226.621us	50	50	100.00
		lc_ctrl_sec_cm	41.490s	1.077ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	36.030s	226.621us	50	50	100.00
		lc_ctrl_sec_cm	41.490s	1.077ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	36.030s	226.621us	50	50	100.00
		lc_ctrl_sec_cm	41.490s	1.077ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	36.030s	226.621us	50	50	100.00
		lc_ctrl_sec_cm	41.490s	1.077ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	36.030s	226.621us	50	50	100.00
		lc_ctrl_sec_cm	41.490s	1.077ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	36.030s	226.621us	50	50	100.00
		lc_ctrl_sec_cm	41.490s	1.077ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	36.030s	226.621us	50	50	100.00
		lc_ctrl_sec_cm	41.490s	1.077ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	36.030s	226.621us	50	50	100.00
		lc_ctrl_sec_cm	41.490s	1.077ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	15.810s	429.406us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.080s	98.530us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	23.750s	3.698ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	24.670s	624.477us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	24.670s	624.477us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	23.610s	3.384ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	18.430s	517.297us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	18.430s	517.297us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.075h	305.857ms	24	50	48.00
V3		TOTAL			24	50	48.00
		TOTAL			1004	1030	97.48

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.17	97.82	95.66	93.31	100.00	98.52	98.76	96.11

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 24 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.20018883145639530891783567443954282788560021241349828070535709821996612053046
      Line 14008, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 28646102629 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 28646102629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.lc_ctrl_stress_all_with_rand_reset.35920103403222806240795962456184021554560475515284536531580790433460042317970
      Line 3328, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5836292656 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 5836292656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 22 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 2.lc_ctrl_stress_all_with_rand_reset.93170375591962983259841145396588570694858413650633110779746557788693254602057
      Line 27169, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 45643222287 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 45643222287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 30.lc_ctrl_stress_all_with_rand_reset.109240188610105253344872557411725841937262779953536978588125733833219156761181
      Line 37307, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

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