LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Sunday May 26 2024 19:04:10 UTC

GitHub Revision: 2cf28c40e5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 76231542290686940289653487239061276463019235878731279188279352215076078972419

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	10.030s	495.320us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.280s	20.786us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.110s	62.660us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.970s	372.135us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.850s	38.621us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.400s	30.529us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.110s	62.660us	20	20	100.00
		lc_ctrl_csr_aliasing	1.850s	38.621us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	11.160s	121.008us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	21.200s	666.232us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.970s	72.523us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.640s	271.722us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	38.160s	1.696ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	25.380s	2.815ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	38.160s	1.696ms	50	50	100.00
		lc_ctrl_prog_failure	5.640s	271.722us	50	50	100.00
		lc_ctrl_errors	25.380s	2.815ms	50	50	100.00
		lc_ctrl_security_escalation	14.940s	388.491us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.698m	2.778ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	24.110s	863.499us	20	20	100.00
		lc_ctrl_jtag_errors	1.546m	3.473ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	18.780s	776.316us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	29.220s	6.622ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	24.110s	863.499us	20	20	100.00
		lc_ctrl_jtag_errors	1.546m	3.473ms	20	20	100.00
		lc_ctrl_jtag_access	21.920s	1.797ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	39.380s	5.289ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	2.900s	190.988us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.690s	83.954us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	26.400s	1.206ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	15.060s	6.956ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.880s	177.736us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	3.420s	212.441us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.230s	162.507us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	16.160s	644.863us	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.090s	12.522us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	9.026m	20.668ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.400s	27.081us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.460s	1.221ms	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.460s	1.221ms	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.280s	20.786us	5	5	100.00
		lc_ctrl_csr_rw	1.110s	62.660us	20	20	100.00
		lc_ctrl_csr_aliasing	1.850s	38.621us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.490s	153.947us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.280s	20.786us	5	5	100.00
		lc_ctrl_csr_rw	1.110s	62.660us	20	20	100.00
		lc_ctrl_csr_aliasing	1.850s	38.621us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.490s	153.947us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	38.790s	234.309us	5	5	100.00
		lc_ctrl_tl_intg_err	4.610s	144.567us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.610s	144.567us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	21.200s	666.232us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	38.160s	1.696ms	50	50	100.00
		lc_ctrl_sec_cm	38.790s	234.309us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	38.160s	1.696ms	50	50	100.00
		lc_ctrl_sec_cm	38.790s	234.309us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	38.160s	1.696ms	50	50	100.00
		lc_ctrl_sec_cm	38.790s	234.309us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	38.160s	1.696ms	50	50	100.00
		lc_ctrl_sec_cm	38.790s	234.309us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	38.160s	1.696ms	50	50	100.00
		lc_ctrl_sec_cm	38.790s	234.309us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	38.160s	1.696ms	50	50	100.00
		lc_ctrl_sec_cm	38.790s	234.309us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	38.160s	1.696ms	50	50	100.00
		lc_ctrl_sec_cm	38.790s	234.309us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	38.160s	1.696ms	50	50	100.00
		lc_ctrl_sec_cm	38.790s	234.309us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	14.940s	388.491us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.160s	121.008us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	29.220s	6.622ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	23.260s	857.305us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	23.260s	857.305us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	24.640s	5.496ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	15.460s	904.097us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	15.460s	904.097us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	2.542h	98.714ms	21	50	42.00
V3		TOTAL			21	50	42.00
		TOTAL			1001	1030	97.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.93	97.82	96.12	93.31	97.62	98.52	99.00	96.11

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 23 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.66131077575283317195582382978035810026809826412862918104719990826938900896358
      Line 15502, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6731973360 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 6731973360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.lc_ctrl_stress_all_with_rand_reset.38038905285456006082318849432043794919256216601503668459262551342112639143423
      Line 19866, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 26210759815 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 26210759815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 21 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 3 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 25.lc_ctrl_stress_all_with_rand_reset.101987050868681921597544210343501048057159066570203483409722976375416140766276
      Line 32639, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 649755946973 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 649755946973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 35.lc_ctrl_stress_all_with_rand_reset.24578822470153228823052136335078937880091443159804485392648286724754254235094
      Line 13415, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 29633847942 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 29633847942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• Error-[CNST-STOF] Constraint solver timeout failure has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 27.lc_ctrl_stress_all_with_rand_reset.108625724181927675481712859838686549838629072769073366323003348531677021331237
      Line 73279, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • 43.lc_ctrl_stress_all_with_rand_reset.104650794814377664011639929296555039149860272928219309494400633379704996170535
      Line 33694, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 37.lc_ctrl_stress_all_with_rand_reset.90807498245016361763753758247792046518183514870434107814094170232011032721395
      Line 35091, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 44737730727 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 44737730727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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