LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Tuesday May 28 2024 19:30:06 UTC

GitHub Revision: 0e5093d709

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 51604449886868634540233838791789448907774502353938218657919214072353062987195

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	8.570s	1.107ms	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.320s	22.090us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.130s	16.622us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.110s	51.432us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.410s	16.933us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.300s	109.036us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.130s	16.622us	20	20	100.00
		lc_ctrl_csr_aliasing	1.410s	16.933us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	12.360s	101.287us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	24.930s	362.620us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.010s	10.403us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	6.220s	354.584us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	40.200s	652.042us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	21.500s	436.721us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	40.200s	652.042us	50	50	100.00
		lc_ctrl_prog_failure	6.220s	354.584us	50	50	100.00
		lc_ctrl_errors	21.500s	436.721us	50	50	100.00
		lc_ctrl_security_escalation	15.550s	1.240ms	50	50	100.00
		lc_ctrl_jtag_state_failure	2.320m	4.073ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	20.430s	810.009us	20	20	100.00
		lc_ctrl_jtag_errors	1.129m	19.384ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	13.560s	7.174ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	36.190s	1.075ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	20.430s	810.009us	20	20	100.00
		lc_ctrl_jtag_errors	1.129m	19.384ms	20	20	100.00
		lc_ctrl_jtag_access	23.820s	4.288ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	28.830s	6.455ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.130s	657.789us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.200s	336.068us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	28.640s	1.340ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	17.960s	3.005ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.610s	131.428us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	7.030s	294.724us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.120s	123.342us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	8.740s	15.526ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.300s	18.730us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	10.290m	74.262ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.430s	29.741us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.630s	159.937us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.630s	159.937us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.320s	22.090us	5	5	100.00
		lc_ctrl_csr_rw	1.130s	16.622us	20	20	100.00
		lc_ctrl_csr_aliasing	1.410s	16.933us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.940s	42.562us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.320s	22.090us	5	5	100.00
		lc_ctrl_csr_rw	1.130s	16.622us	20	20	100.00
		lc_ctrl_csr_aliasing	1.410s	16.933us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.940s	42.562us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	41.330s	2.434ms	5	5	100.00
		lc_ctrl_tl_intg_err	4.890s	488.230us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.890s	488.230us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	24.930s	362.620us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	40.200s	652.042us	50	50	100.00
		lc_ctrl_sec_cm	41.330s	2.434ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	40.200s	652.042us	50	50	100.00
		lc_ctrl_sec_cm	41.330s	2.434ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	40.200s	652.042us	50	50	100.00
		lc_ctrl_sec_cm	41.330s	2.434ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	40.200s	652.042us	50	50	100.00
		lc_ctrl_sec_cm	41.330s	2.434ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	40.200s	652.042us	50	50	100.00
		lc_ctrl_sec_cm	41.330s	2.434ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	40.200s	652.042us	50	50	100.00
		lc_ctrl_sec_cm	41.330s	2.434ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	40.200s	652.042us	50	50	100.00
		lc_ctrl_sec_cm	41.330s	2.434ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	40.200s	652.042us	50	50	100.00
		lc_ctrl_sec_cm	41.330s	2.434ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	15.550s	1.240ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	12.360s	101.287us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	36.190s	1.075ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	22.280s	2.980ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	22.280s	2.980ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	26.630s	10.409ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	21.850s	1.275ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	21.850s	1.275ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	2.659h	40.890ms	18	50	36.00
V3		TOTAL			18	50	36.00
		TOTAL			998	1030	96.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.17	97.82	95.93	93.31	100.00	98.52	98.51	96.11

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 26 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 26 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.9663310384544420508061300495879964234842462553851944088576464377030796817920
      Line 31840, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 23859874397 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 23859874397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.lc_ctrl_stress_all_with_rand_reset.16078045313478517776854636170230234853717980618852330427777416016229442521251
      Line 3744, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 15708215192 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 15708215192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 24 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 3 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 7.lc_ctrl_stress_all_with_rand_reset.14746995345759899784959852770350364985099117917450845169729341454675931957185
      Line 9126, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5236706874 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 5236706874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 10.lc_ctrl_stress_all_with_rand_reset.102923679996942529275577833144631583658499698963122474447837634437550408437266
      Line 2516, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1789140254 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 1789140254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• Error-[CNST-STOF] Constraint solver timeout failure has 3 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 12.lc_ctrl_stress_all_with_rand_reset.94864602444625100993519636291901006660589906680240349239466210683885962498604
      Line 34549, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • 13.lc_ctrl_stress_all_with_rand_reset.30375648600816176449086500002576494506415563655216912730112889789500688122572
      Line 26278, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • ... and 1 more failures.

Past Results

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