LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Thursday May 30 2024 19:02:59 UTC

GitHub Revision: 8cb25a6867

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 26638040090898561482658723926798947801831709189350919955228328310045202344042

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	7.250s	128.197us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.270s	66.132us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.140s	16.658us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.590s	128.472us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.810s	37.096us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.980s	27.037us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.140s	16.658us	20	20	100.00
		lc_ctrl_csr_aliasing	1.810s	37.096us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	9.990s	85.771us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	22.270s	783.076us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.950s	43.196us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.580s	108.605us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	36.980s	1.649ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	21.850s	1.761ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	36.980s	1.649ms	50	50	100.00
		lc_ctrl_prog_failure	4.580s	108.605us	50	50	100.00
		lc_ctrl_errors	21.850s	1.761ms	50	50	100.00
		lc_ctrl_security_escalation	15.970s	478.800us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.566m	11.546ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	10.180s	314.637us	20	20	100.00
		lc_ctrl_jtag_errors	1.737m	4.013ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	15.430s	2.069ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	36.650s	4.744ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	10.180s	314.637us	20	20	100.00
		lc_ctrl_jtag_errors	1.737m	4.013ms	20	20	100.00
		lc_ctrl_jtag_access	23.740s	2.834ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	33.650s	16.837ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	5.030s	188.979us	10	10	100.00
		lc_ctrl_jtag_csr_rw	4.040s	158.239us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	50.800s	2.475ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	31.460s	6.069ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.930s	134.337us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	7.630s	600.880us	10	10	100.00
		lc_ctrl_jtag_alert_test	1.840s	311.477us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	16.690s	1.970ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.120s	15.388us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	10.125m	18.539ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.430s	28.055us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.960s	574.137us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.960s	574.137us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.270s	66.132us	5	5	100.00
		lc_ctrl_csr_rw	1.140s	16.658us	20	20	100.00
		lc_ctrl_csr_aliasing	1.810s	37.096us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.180s	51.255us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.270s	66.132us	5	5	100.00
		lc_ctrl_csr_rw	1.140s	16.658us	20	20	100.00
		lc_ctrl_csr_aliasing	1.810s	37.096us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.180s	51.255us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	34.400s	219.552us	5	5	100.00
		lc_ctrl_tl_intg_err	4.420s	126.707us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.420s	126.707us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	22.270s	783.076us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	36.980s	1.649ms	50	50	100.00
		lc_ctrl_sec_cm	34.400s	219.552us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	36.980s	1.649ms	50	50	100.00
		lc_ctrl_sec_cm	34.400s	219.552us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	36.980s	1.649ms	50	50	100.00
		lc_ctrl_sec_cm	34.400s	219.552us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	36.980s	1.649ms	50	50	100.00
		lc_ctrl_sec_cm	34.400s	219.552us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	36.980s	1.649ms	50	50	100.00
		lc_ctrl_sec_cm	34.400s	219.552us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	36.980s	1.649ms	50	50	100.00
		lc_ctrl_sec_cm	34.400s	219.552us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	36.980s	1.649ms	50	50	100.00
		lc_ctrl_sec_cm	34.400s	219.552us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	36.980s	1.649ms	50	50	100.00
		lc_ctrl_sec_cm	34.400s	219.552us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	15.970s	478.800us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	9.990s	85.771us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	36.650s	4.744ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	22.640s	2.804ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	22.640s	2.804ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	27.100s	14.144ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	19.490s	588.780us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	19.490s	588.780us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	2.469h	130.031ms	24	50	48.00
V3		TOTAL			24	50	48.00
		TOTAL			1003	1030	97.38

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.89	97.82	96.03	93.31	97.62	98.52	99.00	95.94

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 22 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 22 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.100248457504838544875277608925270911078543216145184359847940423206886387517652
      Line 582, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4367928871 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 4367928871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.lc_ctrl_stress_all_with_rand_reset.4789491644457178388585389606044910480997203293077381825173690512893109819091
      Line 14071, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 10591058258 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 10591058258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 20 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 3 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 5.lc_ctrl_stress_all_with_rand_reset.100189430891093675565109100692396634291450659440613384623209153952320039237705
      Line 13357, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 89678592938 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 89678592938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 48.lc_ctrl_stress_all_with_rand_reset.79171204749048634708370598683389331356989883669775895911678093496628763631577
      Line 34700, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 109086502773 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 109086502773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_stress_all has 1 failures.

    • 9.lc_ctrl_stress_all.59475778965504594518112311186701382904550178233966306969123592921603164154192
      Line 16363, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 14829972280 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 14829972280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 18.lc_ctrl_stress_all_with_rand_reset.30933408466648898180807688459924858821293361532751018795815169508845872828877
      Line 49639, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 130030792938 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 130030792938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 31.lc_ctrl_stress_all_with_rand_reset.33177224090905840898067871330807986238165388092235106718606354164348815615783
      Line 39044, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 17930342946 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 17930342946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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