LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Sunday June 02 2024 19:02:53 UTC

GitHub Revision: 01a208901a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 50418669159766293903157726892781832882154091083197082086235277423705989875584

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	8.530s	193.533us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.260s	34.377us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.140s	16.463us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.800s	30.641us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.630s	254.866us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.970s	26.563us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.140s	16.463us	20	20	100.00
		lc_ctrl_csr_aliasing	1.630s	254.866us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	11.040s	141.695us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	20.960s	382.892us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.980s	12.971us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.630s	185.451us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	39.750s	1.107ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	25.310s	1.003ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	39.750s	1.107ms	50	50	100.00
		lc_ctrl_prog_failure	4.630s	185.451us	50	50	100.00
		lc_ctrl_errors	25.310s	1.003ms	50	50	100.00
		lc_ctrl_security_escalation	14.660s	1.531ms	50	50	100.00
		lc_ctrl_jtag_state_failure	2.145m	15.134ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	14.280s	1.722ms	20	20	100.00
		lc_ctrl_jtag_errors	2.038m	57.592ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	15.960s	3.463ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	35.330s	4.505ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	14.280s	1.722ms	20	20	100.00
		lc_ctrl_jtag_errors	2.038m	57.592ms	20	20	100.00
		lc_ctrl_jtag_access	17.790s	713.554us	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	38.540s	1.370ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.190s	214.145us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.560s	224.813us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	48.750s	9.607ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	10.510s	441.901us	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.470s	151.472us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	7.600s	1.122ms	10	10	100.00
		lc_ctrl_jtag_alert_test	2.100s	234.097us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	23.230s	1.000ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.130s	13.822us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	6.295m	99.089ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.470s	103.093us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.460s	413.178us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.460s	413.178us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.260s	34.377us	5	5	100.00
		lc_ctrl_csr_rw	1.140s	16.463us	20	20	100.00
		lc_ctrl_csr_aliasing	1.630s	254.866us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.120s	256.229us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.260s	34.377us	5	5	100.00
		lc_ctrl_csr_rw	1.140s	16.463us	20	20	100.00
		lc_ctrl_csr_aliasing	1.630s	254.866us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.120s	256.229us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	39.090s	1.441ms	5	5	100.00
		lc_ctrl_tl_intg_err	5.360s	2.178ms	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	5.360s	2.178ms	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	20.960s	382.892us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	39.750s	1.107ms	50	50	100.00
		lc_ctrl_sec_cm	39.090s	1.441ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	39.750s	1.107ms	50	50	100.00
		lc_ctrl_sec_cm	39.090s	1.441ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	39.750s	1.107ms	50	50	100.00
		lc_ctrl_sec_cm	39.090s	1.441ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	39.750s	1.107ms	50	50	100.00
		lc_ctrl_sec_cm	39.090s	1.441ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	39.750s	1.107ms	50	50	100.00
		lc_ctrl_sec_cm	39.090s	1.441ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	39.750s	1.107ms	50	50	100.00
		lc_ctrl_sec_cm	39.090s	1.441ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	39.750s	1.107ms	50	50	100.00
		lc_ctrl_sec_cm	39.090s	1.441ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	39.750s	1.107ms	50	50	100.00
		lc_ctrl_sec_cm	39.090s	1.441ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	14.660s	1.531ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.040s	141.695us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	35.330s	4.505ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	28.330s	692.720us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	28.330s	692.720us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	21.650s	1.763ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	20.530s	3.136ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	20.530s	3.136ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	25.020m	54.966ms	24	50	48.00
V3		TOTAL			24	50	48.00
		TOTAL			1004	1030	97.48

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.18	97.82	95.84	93.31	100.00	98.52	98.51	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 21 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 21 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.61691009265980575437420170728162854518165982352309148390657460721735933747004
      Line 6776, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 17888238924 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 17888238924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 5.lc_ctrl_stress_all_with_rand_reset.69426334155968899476011612927660923050777407935410853122068512276124232687123
      Line 9273, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 13716398300 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 13716398300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 19 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 5 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 5 failures.

    • 11.lc_ctrl_stress_all_with_rand_reset.60320496577710301613565653849256093392214268121908198337910551958611038207212
      Line 17604, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 12343116736 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 12343116736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 20.lc_ctrl_stress_all_with_rand_reset.1728607720679025445586374364891504817703512807283175485108646992025211211646
      Line 6742, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 51796861927 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 51796861927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 3 more failures.

Past Results

• Latest
• 2024.05.31_04.46.01
• 2024.05.29_03.14.20
• 2024.05.27_04.22.29
• 2024.05.24_04.27.23
• 2024.05.22_04.25.26
• 2024.05.20_03.58.10
• 2024.05.17_06.26.17