LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Tuesday June 04 2024 19:02:20 UTC

GitHub Revision: a182fcef27

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 115716131103921631007013649731972014580281041353363476420230431751664670300928

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	8.390s	120.925us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.280s	37.366us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.150s	17.627us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.870s	49.873us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.450s	55.379us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.170s	123.134us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.150s	17.627us	20	20	100.00
		lc_ctrl_csr_aliasing	1.450s	55.379us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.670s	79.998us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	18.280s	271.861us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.020s	13.774us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.270s	84.793us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	37.230s	395.104us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	25.510s	1.705ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	37.230s	395.104us	50	50	100.00
		lc_ctrl_prog_failure	4.270s	84.793us	50	50	100.00
		lc_ctrl_errors	25.510s	1.705ms	50	50	100.00
		lc_ctrl_security_escalation	16.950s	462.619us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.622m	4.200ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	20.260s	696.732us	20	20	100.00
		lc_ctrl_jtag_errors	1.411m	25.011ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	12.460s	496.747us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	33.480s	3.072ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	20.260s	696.732us	20	20	100.00
		lc_ctrl_jtag_errors	1.411m	25.011ms	20	20	100.00
		lc_ctrl_jtag_access	23.540s	1.033ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	34.390s	2.732ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.170s	108.605us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.980s	145.464us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	26.710s	4.915ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	23.510s	8.783ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.080s	52.815us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	5.850s	209.579us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.600s	173.874us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	13.640s	902.385us	9	10	90.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.550s	102.305us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	7.442m	13.024ms	48	50	96.00
V2	alert_test	lc_ctrl_alert_test	1.400s	30.276us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.020s	3.062ms	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.020s	3.062ms	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.280s	37.366us	5	5	100.00
		lc_ctrl_csr_rw	1.150s	17.627us	20	20	100.00
		lc_ctrl_csr_aliasing	1.450s	55.379us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.990s	39.698us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.280s	37.366us	5	5	100.00
		lc_ctrl_csr_rw	1.150s	17.627us	20	20	100.00
		lc_ctrl_csr_aliasing	1.450s	55.379us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.990s	39.698us	20	20	100.00
V2		TOTAL			697	700	99.57
V2S	tl_intg_err	lc_ctrl_sec_cm	34.780s	224.779us	5	5	100.00
		lc_ctrl_tl_intg_err	4.540s	278.172us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.540s	278.172us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	18.280s	271.861us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	37.230s	395.104us	50	50	100.00
		lc_ctrl_sec_cm	34.780s	224.779us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	37.230s	395.104us	50	50	100.00
		lc_ctrl_sec_cm	34.780s	224.779us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	37.230s	395.104us	50	50	100.00
		lc_ctrl_sec_cm	34.780s	224.779us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	37.230s	395.104us	50	50	100.00
		lc_ctrl_sec_cm	34.780s	224.779us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	37.230s	395.104us	50	50	100.00
		lc_ctrl_sec_cm	34.780s	224.779us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	37.230s	395.104us	50	50	100.00
		lc_ctrl_sec_cm	34.780s	224.779us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	37.230s	395.104us	50	50	100.00
		lc_ctrl_sec_cm	34.780s	224.779us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	37.230s	395.104us	50	50	100.00
		lc_ctrl_sec_cm	34.780s	224.779us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.950s	462.619us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.670s	79.998us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	33.480s	3.072ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	24.620s	652.800us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	24.620s	652.800us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	28.080s	5.646ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	23.210s	1.399ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	23.210s	1.399ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	39.034m	82.901ms	18	50	36.00
V3		TOTAL			18	50	36.00
		TOTAL			995	1030	96.60

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	25	92.59
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.19	97.82	95.84	93.31	100.00	98.52	98.76	96.11

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 30 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 30 failures.

    • 4.lc_ctrl_stress_all_with_rand_reset.59038847636454265803291044191294751124735533528017277727335572309289548531686
      Line 13306, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 42230833439 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 42230833439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 5.lc_ctrl_stress_all_with_rand_reset.54144889165163296208794835122193808177962551805313429101748507345273224846799
      Line 20305, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 18576047608 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 18576047608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 28 more failures.

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 18.lc_ctrl_stress_all_with_rand_reset.104108524587197015360726581680795416404749479046404324799619551031788877446264
      Line 22944, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 61445929002 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 61445929002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 43.lc_ctrl_stress_all_with_rand_reset.93689034295354030486379429153647757868598678466040435714025271512168690799758
      Line 52262, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 82900534764 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 82900534764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (lc_ctrl_jtag_priority_vseq.sv:113) [lc_ctrl_jtag_priority_vseq] timeout occurred! has 1 failures:

  • Test lc_ctrl_jtag_priority has 1 failures.

    • 0.lc_ctrl_jtag_priority.14150218756991534089308991990100738129296576396936003212660560728644468260956
      Line 473, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_priority/latest/run.log

        UVM_FATAL @ 10010382922 ps: (lc_ctrl_jtag_priority_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.lc_ctrl_jtag_priority_vseq] timeout occurred!
        UVM_INFO @ 10010382922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all has 1 failures.

    • 21.lc_ctrl_stress_all.63594869333087776268214241948193481163909634694202741083832638934664649657079
      Line 644, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 1288982633 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 1288982633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_stress_all has 1 failures.

    • 40.lc_ctrl_stress_all.65941500801540571939635628657973172784341639870504761808461970718715638375533
      Line 2481, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 4617846909 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 4617846909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.06.03_06.54.07
• 2024.05.31_04.46.01
• 2024.05.29_03.14.20
• 2024.05.27_04.22.29
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